Lines Matching refs:msk
70 u32 reg, msk, val;
75 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
80 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
85 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
86 val = enable ? msk : 0;
90 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
95 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
100 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
105 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
106 val = enable ? msk : 0;
111 regmap_update_bits(ssusb->uwk, reg, msk, val);