usb/host/xhci.h

81  * 			supports.  If bit n is set, the HC supports a page size
84  * @cmd_ring:		CRP - 64-bit Command Ring Pointer
85  * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
126  * The xHCI driver must reinitialize the xHC after setting this bit.
147 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
159 /* HC not running - set to 1 when run/stop bit is cleared. */
161 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
183  * notification type that matches a bit set in this bit field.
193 /* bit 0 is the command ring cycle state */
201 /* Command Ring pointer - bit mask for the lower 32 bits. */
207 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
209 /* bit 9: Configuration Information Enable, xhci 1.1 */
226  * "updates the Cycle bit in the TRBs to indicate to software the current
280  * "Software should read and write these registers using only Dword (32 bit)
357 /* bit 24 reserved */
358 /* Is this LS/FS device connected through a HS hub? - bit 25 */
360 /* Set if the device is a hub - bit 26 */
414  * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
457 /* bit 15 is Linear Stream Array */
486 /* bit 6 reserved */
487 /* bit 7 is Host Initiate Disable - for disabling stream selection */
509  * @drop_context:	set the bit of the endpoint context you want to disable
510  * @add_context:	set the bit of the endpoint context you want to enable
548 	/* 64-bit stream ring address, cycle state, and stream type */
614 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
785  * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
788 	/* 64-bit device addresses; we only write 32-bit addresses */
793 /* TODO: write function to set the 64-bit device DMA address */
801 	/* 64-bit buffer address, or immediate data */
808 /* Transfer event TRB length bit mask */
812 /** Transfer Event bit fields **/
936 	/* 64-bit segment pointer*/
1030 /* Cycle bit - indicates TRB ownership by HC or HCD */
1078 /* TRB bit mask */
1367 	/* 64-bit event ring segment address */
1734  * Some xHCI implementations may support 64-bit address pointers.  Registers
1735  * with 64-bit address pointers should be written to with dword accesses by
1737  * xHCI implementations that do not support 64-bit address pointers will ignore
2219 	unsigned int	bit;
2226 		for_each_set_bit(bit, &drop, 32)
2228 				       bit / 2,
2229 				       bit % 2 ? "in":"out");
2238 		for_each_set_bit(bit, &add, 32)
2240 				       bit / 2,
2241 				       bit % 2 ? "in":"out");