usb/host/xhci.c

304 		struct xhci_intr_reg __iomem *ir;
306 		ir = &xhci->run_regs->ir_set[i];
307 		val = xhci_read_64(xhci, &ir->erst_base);
309 			xhci_write_64(xhci, 0, &ir->erst_base);
310 		val= xhci_read_64(xhci, &ir->erst_dequeue);
312 			xhci_write_64(xhci, 0, &ir->erst_dequeue);
323 static int xhci_enable_interrupter(struct xhci_interrupter *ir)
327 	if (!ir || !ir->ir_set)
330 	iman = readl(&ir->ir_set->irq_pending);
331 	writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
336 static int xhci_disable_interrupter(struct xhci_interrupter *ir)
340 	if (!ir || !ir->ir_set)
343 	iman = readl(&ir->ir_set->irq_pending);
344 	writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
350 static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
355 	if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)
358 	imod = readl(&ir->ir_set->irq_control);
361 	writel(imod, &ir->ir_set->irq_control);
500 	struct xhci_interrupter *ir = xhci->interrupters[0];
516 	xhci_enable_interrupter(ir);
551 	struct xhci_interrupter *ir = xhci->interrupters[0];
558 		ir->ip_autoclear = true;
565 	temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
570 	xhci_set_interrupter_moderation(ir, xhci->imod_interval);
613 	struct xhci_interrupter *ir = xhci->interrupters[0];
648 	xhci_disable_interrupter(ir);
709 	struct xhci_interrupter *ir;
720 		ir = xhci->interrupters[i];
721 		if (!ir)
724 		ir->s3_erst_size = readl(&ir->ir_set->erst_size);
725 		ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
726 		ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
727 		ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
728 		ir->s3_irq_control = readl(&ir->ir_set->irq_control);
734 	struct xhci_interrupter *ir;
744 		ir = xhci->interrupters[i];
745 		if (!ir)
748 		writel(ir->s3_erst_size, &ir->ir_set->erst_size);
749 		xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
750 		xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
751 		writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
752 		writel(ir->s3_irq_control, &ir->ir_set->irq_control);