gadget/udc/renesas_usbf.c

344 	/* ep0: buf @0x0000 64 bytes, fixed 32 words */
345 	[0] = USBF_EP_INFO("ep0-ctrl",
547 static void usbf_ep0_send_null(struct usbf_ep *ep0, bool is_data1)
555 	usbf_ep_reg_bitset(ep0, USBF_REG_EP0_CONTROL, set);
558 static int usbf_ep0_pio_in(struct usbf_ep *ep0, struct usbf_req *req)
571 				dev_dbg(ep0->udc->dev, "ep0 send null\n");
572 				usbf_ep0_send_null(ep0, false);
576 			if ((req->req.actual % ep0->ep.maxpacket) == 0) {
578 					dev_dbg(ep0->udc->dev, "ep0 send null\n");
579 					usbf_ep0_send_null(ep0, false);
588 	if (left > ep0->ep.maxpacket)
589 		left = ep0->ep.maxpacket;
596 		usbf_ep_reg_write_rep(ep0, USBF_REG_EP0_WRITE, buf, nb);
601 	ctrl = usbf_ep_reg_readl(ep0, USBF_REG_EP0_CONTROL);
605 		usbf_ep_reg_writel(ep0, USBF_REG_EP0_WRITE, last);
609 	usbf_ep_reg_writel(ep0, USBF_REG_EP0_CONTROL, ctrl | USBF_EP0_DEND);
611 	dev_dbg(ep0->udc->dev, "ep0 send %u/%u\n",
617 static int usbf_ep0_pio_out(struct usbf_ep *ep0, struct usbf_req *req)
627 	if (ep0->status & USBF_EP0_OUT_INT) {
628 		recv = usbf_ep_reg_readl(ep0, USBF_REG_EP0_LENGTH) & USBF_EP0_LDATA;
636 		dev_dbg(ep0->udc->dev, "ep0 recv %u, left %u\n", count, left);
638 		if (left > ep0->ep.maxpacket)
639 			left = ep0->ep.maxpacket;
649 				usbf_ep_reg_read_rep(ep0, USBF_REG_EP0_READ,
656 				last = usbf_ep_reg_readl(ep0, USBF_REG_EP0_READ);
661 		dev_dbg(ep0->udc->dev, "ep0 recv %u/%u\n",
665 			dev_dbg(ep0->udc->dev, "ep0 req.status=%d\n", req_status);
670 		if (recv < ep0->ep.maxpacket) {
671 			dev_dbg(ep0->udc->dev, "ep0 short packet\n");
689 	if (ep0->status & USBF_EP0_OUT_NULL_INT) {
691 		dev_dbg(ep0->udc->dev, "ep0 null packet\n");
704 static void usbf_ep0_fifo_flush(struct usbf_ep *ep0)
709 	usbf_ep_reg_bitset(ep0, USBF_REG_EP0_CONTROL, USBF_EP0_BCLR);
711 	ret = readl_poll_timeout_atomic(ep0->regs + USBF_REG_EP0_STATUS, sts,
715 		dev_err(ep0->udc->dev, "ep0 flush fifo timed out\n");
1785 static void usbf_ep0_enable(struct usbf_ep *ep0)
1787 	usbf_ep_reg_writel(ep0, USBF_REG_EP0_CONTROL, USBF_EP0_INAK_EN | USBF_EP0_BCLR);
1789 	usbf_ep_reg_writel(ep0, USBF_REG_EP0_INT_ENA,
1793 	ep0->udc->ep0state = EP0_IDLE;
1794 	ep0->disabled = 0;
1796 	/* enable interrupts for the ep0 */
1797 	usbf_reg_bitset(ep0->udc, USBF_REG_USB_INT_ENA, USBF_USB_EPN_EN(0));
1916 static int usbf_ep0_queue(struct usbf_ep *ep0, struct usbf_req *req,
1925 	list_add_tail(&req->queue, &ep0->queue);
1927 	if (ep0->udc->ep0state == EP0_IN_STATUS_START_PHASE)
1930 	if (!ep0->is_in)
1933 	if (ep0->udc->ep0state == EP0_IN_STATUS_PHASE) {
1935 			dev_err(ep0->udc->dev,
1936 				"request lng %u for ep0 in status phase\n",
1940 		ep0->delayed_status = 0;
1942 	if (!ep0->is_processing) {
1943 		ret = usbf_ep0_pio_in(ep0, req);
1945 			dev_err(ep0->udc->dev,
2049 		/* We dequeue a request on ep0. On this endpoint, we can have
2176 static void usbf_ep0_fill_req(struct usbf_ep *ep0, struct usbf_req *req,
2182 		memcpy(ep0->udc->ep0_buf, buf, length);
2184 	req->req.buf = ep0->udc->ep0_buf;
2329 			 * Returning an error code leads to a STALL on this ep0
2444 static int usbf_handle_ep0_setup(struct usbf_ep *ep0)
2450 	struct usbf_udc *udc = ep0->udc;
2457 	dev_dbg(ep0->udc->dev,
2458 		"ep0 req%02x.%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\n",
2466 			usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2469 			ep0->is_in = 1;
2472 			usbf_ep_reg_bitclr(ep0, USBF_REG_EP0_CONTROL,
2474 			ep0->is_in = 0;
2478 		ep0->is_in = 1;
2482 	ep0->delayed_status = 0;
2520 static int usbf_handle_ep0_data_status(struct usbf_ep *ep0,
2524 	struct usbf_udc *udc = ep0->udc;
2527 	ret = usbf_ep_process_queue(ep0);
2531 			"no request available for ep0 %s phase\n",
2544 			"process queue failed for ep0 %s phase (%d)\n",
2551 static int usbf_handle_ep0_out_status_start(struct usbf_ep *ep0)
2553 	struct usbf_udc *udc = ep0->udc;
2556 	usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2559 	ep0->is_in = 0;
2561 	req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2563 		usbf_ep0_fill_req(ep0, &udc->setup_reply, NULL, 0, NULL);
2564 		usbf_ep0_queue(ep0, &udc->setup_reply, GFP_ATOMIC);
2568 				"queued request length %u for ep0 out status phase\n",
2576 static int usbf_handle_ep0_in_status_start(struct usbf_ep *ep0)
2578 	struct usbf_udc *udc = ep0->udc;
2582 	usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2585 	ep0->is_in = 1;
2588 	req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2590 		if (ep0->delayed_status) {
2591 			dev_dbg(ep0->udc->dev,
2592 				"EP0_IN_STATUS_START_PHASE ep0->delayed_status set\n");
2597 		usbf_ep0_fill_req(ep0, &udc->setup_reply, NULL,
2599 		usbf_ep0_queue(ep0, &udc->setup_reply,
2602 		req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2606 				"queued request length %u for ep0 in status phase\n",
2611 	ret = usbf_ep0_pio_in(ep0, req);
2613 		usbf_ep_req_done(ep0, req, ret);
2622 static void usbf_ep0_interrupt(struct usbf_ep *ep0)
2624 	struct usbf_udc *udc = ep0->udc;
2629 	ep0->status = usbf_ep_reg_readl(ep0, USBF_REG_EP0_STATUS);
2630 	usbf_ep_reg_writel(ep0, USBF_REG_EP0_STATUS, ~ep0->status);
2632 	dev_dbg(ep0->udc->dev, "ep0 status=0x%08x, enable=%08x\n, ctrl=0x%08x\n",
2633 		ep0->status,
2634 		usbf_ep_reg_readl(ep0, USBF_REG_EP0_INT_ENA),
2635 		usbf_ep_reg_readl(ep0, USBF_REG_EP0_CONTROL));
2637 	sts = ep0->status & (USBF_EP0_SETUP_INT | USBF_EP0_IN_INT | USBF_EP0_OUT_INT |
2643 		dev_dbg(ep0->udc->dev, "udc->ep0state=%d\n", udc->ep0state);
2653 			dev_dbg(ep0->udc->dev, "ep0 handle setup\n");
2654 			ret = usbf_handle_ep0_setup(ep0);
2662 			dev_dbg(ep0->udc->dev, "ep0 handle in data phase\n");
2663 			ret = usbf_handle_ep0_data_status(ep0,
2672 			dev_dbg(ep0->udc->dev, "ep0 handle out status start phase\n");
2673 			ret = usbf_handle_ep0_out_status_start(ep0);
2681 			dev_dbg(ep0->udc->dev, "ep0 handle out status phase\n");
2682 			ret = usbf_handle_ep0_data_status(ep0,
2692 			dev_dbg(ep0->udc->dev, "ep0 handle out status end phase\n");
2701 			dev_dbg(ep0->udc->dev, "ep0 handle out data phase\n");
2702 			ret = usbf_handle_ep0_data_status(ep0,
2711 			dev_dbg(ep0->udc->dev, "ep0 handle in status start phase\n");
2712 			ret = usbf_handle_ep0_in_status_start(ep0);
2720 			dev_dbg(ep0->udc->dev, "ep0 handle in status phase\n");
2721 			ret = usbf_handle_ep0_data_status(ep0,
2730 			dev_dbg(ep0->udc->dev, "ep0 handle in status end\n");
2740 			dev_dbg(ep0->udc->dev, "ep0 failed (%d)\n", ret);
2745 			usbf_ep_stall(ep0, true);
2748 			usbf_ep_nuke(ep0, -EPROTO);
2756 	dev_dbg(ep0->udc->dev, "ep0 done udc->ep0state=%d, status=0x%08x. next=0x%08x\n",
2758 		usbf_ep_reg_readl(ep0, USBF_REG_EP0_STATUS));
3285 	udc->gadget.ep0 = &udc->ep[0].ep;