Lines Matching refs:ep0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
209 /* we share one TRB for ep0/1 */
864 struct dwc3_ep *ep0;
871 ep0 = dwc->eps[0];
875 trace_dwc3_complete_trb(ep0, trb);
877 r = next_request(&ep0->pending_list);
885 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
896 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
900 trace_dwc3_complete_trb(ep0, trb);
913 dwc3_gadget_giveback(ep0, r, 0);
1111 * For status/DATA OUT stage, TRB will be queued on ep0 out
1113 * queuing ENDXFER command for ep0 out endpoint.