Lines Matching refs:period
377 * dwc3_ref_clk_period - Reference clock period configuration
378 * Default reference clock period depends on hardware
380 * from the default, this will set clock period in DWC3_GUCTL
386 unsigned long period;
396 period = NSEC_PER_SEC / rate;
398 period = dwc->ref_clk_per;
399 rate = NSEC_PER_SEC / period;
406 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
415 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
419 * neither does rate * period).
421 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
423 * the division when calculating rate or period (whichever one was
427 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
1132 * periods fit into a 16KHz clock period. When performing
1710 device_property_read_u32(dev, "snps,ref-clock-period-ns",