usb/dwc2/core.c

41 	dev_dbg(hsotg->dev, "%s\n", __func__);
73 	dev_dbg(hsotg->dev, "%s\n", __func__);
158 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
267 		dev_dbg(hsotg->dev,
271 		dev_dbg(hsotg->dev, "restore done  generated here\n");
508 	dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
557 	dev_dbg(hsotg->dev, "Clearing force mode bits\n");
604 		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
624 	dev_dbg(hsotg->dev, "Host Global Registers\n");
626 	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",
629 	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",
632 	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",
635 	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",
638 	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",
641 	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",
645 		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
650 	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",
654 		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
656 		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",
659 		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",
662 		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",
665 		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",
668 		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",
671 		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",
675 			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",
696 	dev_dbg(hsotg->dev, "Core Global Registers\n");
698 	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",
701 	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",
704 	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",
707 	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",
710 	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",
713 	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",
716 	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",
719 	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",
722 	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",
725 	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",
728 	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",
731 	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",
734 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",
737 	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",
740 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",
743 	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",
746 	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",
749 	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",
752 	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",
755 	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",
758 	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",
761 	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",
764 	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",
767 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",
771 	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",
971 	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
988 		dev_dbg(hsotg->dev, "FS PHY selected\n");
1008 				dev_dbg(hsotg->dev, "Activating transceiver\n");
1028 		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1067 		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1080 		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1149 		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");