usb/chipidea/ci.h

3  * ci.h - common structures, functions, and macros of the ChipIdea driver
84  * @ci: pointer to the controller
102 	struct ci_hdrc				*ci;
138 	void		(*suspend)(struct ci_hdrc *ci);
139 	void		(*resume)(struct ci_hdrc *ci, bool power_lost);
270 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
272 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
273 	return ci->roles[ci->role];
276 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
283 	if (!ci->roles[role])
286 	ret = ci->roles[role]->start(ci);
290 	ci->role = role;
292 	if (ci->usb_phy) {
294 			usb_phy_set_event(ci->usb_phy, USB_EVENT_ID);
297 			usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
303 static inline void ci_role_stop(struct ci_hdrc *ci)
305 	enum ci_role role = ci->role;
310 	ci->role = CI_ROLE_END;
312 	ci->roles[role]->stop(ci);
314 	if (ci->usb_phy)
315 		usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
318 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
320 	if (ci->role == CI_ROLE_HOST)
322 	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
340  * @ci: the controller
346 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
348 	return ioread32(ci->hw_bank.abs + offset) & mask;
353  * @ci: the controller
358 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
362 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
365 	iowrite32(data, ci->hw_bank.abs + offset);
370  * @ci: the controller
376 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
378 	return ioread32(ci->hw_bank.regmap[reg]) & mask;
392 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
395 	if (ci->imx28_write_fix)
403  * @ci: the controller
408 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
412 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
415 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
420  * @ci: the controller
426 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
429 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
431 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
437  * @ci: the controller
444 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
447 	u32 val = hw_read(ci, reg, ~0);
449 	hw_write(ci, reg, mask, data);
457  * @ci: chipidea device
459 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
462 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
464 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
465 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
472 int ci_ulpi_init(struct ci_hdrc *ci);
473 void ci_ulpi_exit(struct ci_hdrc *ci);
474 int ci_ulpi_resume(struct ci_hdrc *ci);
476 u32 hw_read_intr_enable(struct ci_hdrc *ci);
478 u32 hw_read_intr_status(struct ci_hdrc *ci);
480 int hw_device_reset(struct ci_hdrc *ci);
482 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
484 u8 hw_port_test_get(struct ci_hdrc *ci);
486 void hw_phymode_configure(struct ci_hdrc *ci);
488 void ci_platform_configure(struct ci_hdrc *ci);
490 void dbg_create_files(struct ci_hdrc *ci);
492 void dbg_remove_files(struct ci_hdrc *ci);