ufs/host/ufs-sprd.c

23 static struct ufs_sprd_priv *ufs_sprd_get_priv_data(struct ufs_hba *hba)
25 	struct ufs_sprd_host *host = ufshcd_get_variant(hba);
43 static void ufs_sprd_get_unipro_ver(struct ufs_hba *hba)
45 	struct ufs_sprd_host *host = ufshcd_get_variant(hba);
47 	if (ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &host->unipro_ver))
51 static void ufs_sprd_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
53 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
59 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
95 static int ufs_sprd_parse_dt(struct device *dev, struct ufs_hba *hba, struct ufs_sprd_host *host)
132 static int ufs_sprd_common_init(struct ufs_hba *hba)
134 	struct device *dev = hba->dev;
149 	host->hba = hba;
150 	ufshcd_set_variant(hba, host);
152 	hba->caps |= UFSHCD_CAP_CLK_GATING |
155 	hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS;
157 	ret = ufs_sprd_parse_dt(dev, hba, host);
162 static int sprd_ufs_pwr_change_notify(struct ufs_hba *hba,
167 	struct ufs_sprd_host *host = ufshcd_get_variant(hba);
173 			ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx,
180 static int ufs_sprd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
186 		if (ufshcd_is_auto_hibern8_supported(hba)) {
187 			spin_lock_irqsave(hba->host->host_lock, flags);
188 			ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
189 			spin_unlock_irqrestore(hba->host->host_lock, flags);
196 static void ufs_sprd_n6_host_reset(struct ufs_hba *hba)
198 	struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
200 	dev_info(hba->dev, "ufs host reset!\n");
207 static int ufs_sprd_n6_device_reset(struct ufs_hba *hba)
209 	struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
211 	dev_info(hba->dev, "ufs device reset!\n");
220 static void ufs_sprd_n6_key_acc_enable(struct ufs_hba *hba)
228 	val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
230 		ufs_sprd_n6_host_reset(hba);
232 		ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
247 	dev_err(hba->dev, "key reg access enable fail, disable crypto\n");
248 	hba->caps &= ~UFSHCD_CAP_CRYPTO;
251 static int ufs_sprd_n6_init(struct ufs_hba *hba)
256 	ret = ufs_sprd_common_init(hba);
260 	priv = ufs_sprd_get_priv_data(hba);
266 	if (hba->caps & UFSHCD_CAP_CRYPTO)
267 		ufs_sprd_n6_key_acc_enable(hba);
272 static int ufs_sprd_n6_phy_init(struct ufs_hba *hba)
278 	struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
280 	ufshcd_dme_set(hba, UIC_ARG_MIB(CBREFCLKCTRL2), 0x90);
281 	ufshcd_dme_set(hba, UIC_ARG_MIB(CBCRCTRL), 0x01);
282 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL,
284 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL,
286 	ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
287 	ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), 0x01);
295 				ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRLSB), 0x1c);
296 				ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRMSB), offset);
297 				ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRLSB), 0x04);
298 				ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRMSB), 0x00);
299 				ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGRDWRSEL), 0x01);
300 				ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
315 	ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
316 	ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0x0);
322 static int sprd_ufs_n6_hce_enable_notify(struct ufs_hba *hba,
326 	struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
334 		ufs_sprd_n6_host_reset(hba);
336 		if (hba->caps & UFSHCD_CAP_CRYPTO)
337 			ufs_sprd_n6_key_acc_enable(hba);
341 		err = ufs_sprd_n6_phy_init(hba);
343 			dev_err(hba->dev, "Phy setup failed (%d)\n", err);
347 		ufs_sprd_get_unipro_ver(hba);
353 static void sprd_ufs_n6_h8_notify(struct ufs_hba *hba,
357 	struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
365 			ufs_sprd_ctrl_uic_compl(hba, false);
377 			ufs_sprd_ctrl_uic_compl(hba, true);
430 	struct ufs_hba *hba =  platform_get_drvdata(pdev);
433 	ufshcd_remove(hba);