Lines Matching refs:core_clk_ctrl_reg
1220 u32 core_clk_ctrl_reg;
1238 &core_clk_ctrl_reg);
1246 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1247 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1251 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1252 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1256 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1260 core_clk_ctrl_reg);
1292 u32 core_clk_ctrl_reg;
1296 &core_clk_ctrl_reg);
1300 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1301 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1304 core_clk_ctrl_reg);