Lines Matching defs:host
99 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
109 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
112 qcom_ice_enable(host->ice);
115 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
117 struct ufs_hba *hba = host->hba;
130 host->ice = ice;
136 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
138 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
139 return qcom_ice_resume(host->ice);
144 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
146 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
147 return qcom_ice_suspend(host->ice);
156 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
168 return qcom_ice_program_key(host->ice,
174 return qcom_ice_evict_key(host->ice, slot);
181 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
185 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
190 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
195 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
201 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
203 if (!host->is_lane_clks_enabled)
206 clk_bulk_disable_unprepare(host->num_clks, host->clks);
208 host->is_lane_clks_enabled = false;
211 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
215 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
219 host->is_lane_clks_enabled = true;
224 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
227 struct device *dev = host->hba->dev;
232 err = devm_clk_bulk_get_all(dev, &host->clks);
236 host->num_clks = err;
281 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
283 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
285 if (host->hw_ver.major >= 0x05)
286 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
290 * ufs_qcom_host_reset - reset host controller and PHY
295 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
298 if (!host->core_reset)
304 ret = reset_control_assert(host->core_reset);
318 ret = reset_control_deassert(host->core_reset);
335 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
337 if (host->hw_ver.major >= 0x4)
346 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
347 struct ufs_host_params *host_params = &host->host_params;
348 struct phy *phy = host->generic_phy;
357 if (host->hw_ver.major == 0x5) {
358 if (host->phy_gear == UFS_HS_G5)
379 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
391 ufs_qcom_select_unipro_mode(host);
421 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
435 err = ufs_qcom_enable_lane_clks(host);
441 ufs_qcom_ice_enable(host);
454 * @hba: host controller instance
466 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
474 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
477 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
531 * Some UFS devices (and may be host) have issues if LCC is
533 * before link startup which will make sure that both host
549 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
552 if (!host->device_reset)
555 gpiod_set_value_cansleep(host->device_reset, asserted);
561 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
562 struct phy *phy = host->generic_phy;
573 ufs_qcom_disable_lane_clks(host);
580 ufs_qcom_disable_lane_clks(host);
583 return ufs_qcom_ice_suspend(host);
588 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
589 struct phy *phy = host->generic_phy;
600 err = ufs_qcom_enable_lane_clks(host);
605 err = ufs_qcom_enable_lane_clks(host);
610 return ufs_qcom_ice_resume(host);
613 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
615 if (host->dev_ref_clk_ctrl_mmio &&
616 (enable ^ host->is_dev_ref_clk_enabled)) {
617 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
620 temp |= host->dev_ref_clk_en_mask;
622 temp &= ~host->dev_ref_clk_en_mask;
633 gating_wait = host->hba->dev_info.clk_gating_wait_us;
649 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
655 readl(host->dev_ref_clk_ctrl_mmio);
665 host->is_dev_ref_clk_enabled = enable;
669 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
671 struct device *dev = host->hba->dev;
674 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
680 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
689 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
691 struct ufs_pa_layer_attr *p = &host->dev_req_params;
715 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
719 bw_table = ufs_qcom_get_bw_table(host);
721 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
729 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
730 struct ufs_host_params *host_params = &host->host_params;
759 if (host->phy_gear == dev_req_params->gear_tx)
762 host->phy_gear = dev_req_params->gear_tx;
768 ufs_qcom_dev_ref_clk_ctrl(host, true);
770 if (host->hw_ver.major >= 0x4) {
791 memcpy(&host->dev_req_params,
794 ufs_qcom_icc_update_bw(host);
799 ufs_qcom_dev_ref_clk_ctrl(host, false);
844 * @hba: host controller instance
846 * QCOM UFS host controller might have some non standard behaviours (quirks)
848 * quirks to standard UFS host controller driver so standard takes them into
853 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
855 if (host->hw_ver.major == 0x2)
858 if (host->hw_ver.major > 0x3)
862 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
864 struct ufs_host_params *host_params = &host->host_params;
874 host->phy_gear = host_params->hs_tx_gear;
876 if (host->hw_ver.major < 0x4) {
882 host->phy_gear = UFS_HS_G2;
883 } else if (host->hw_ver.major >= 0x5) {
884 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
893 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
900 host->phy_gear = UFS_HS_G4;
906 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
907 struct ufs_host_params *host_params = &host->host_params;
927 * @hba: host controller instance
936 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
943 if (!host)
949 ufs_qcom_icc_update_bw(host);
953 ufs_qcom_dev_ref_clk_ctrl(host, false);
961 ufs_qcom_dev_ref_clk_ctrl(host, true);
963 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
975 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
977 ufs_qcom_assert_reset(host->hba);
986 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
988 ufs_qcom_deassert_reset(host->hba);
1003 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1005 struct device *dev = host->hba->dev;
1008 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1009 if (IS_ERR(host->icc_ddr))
1010 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1013 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1014 if (IS_ERR(host->icc_cpu))
1015 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1023 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1033 * @hba: host controller instance
1045 struct ufs_qcom_host *host;
1048 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1049 if (!host)
1052 /* Make a two way bind between the qcom host and the hba */
1053 host->hba = hba;
1054 ufshcd_set_variant(hba, host);
1057 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1058 if (IS_ERR(host->core_reset)) {
1059 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1065 host->rcdev.of_node = dev->of_node;
1066 host->rcdev.ops = &ufs_qcom_reset_ops;
1067 host->rcdev.owner = dev->driver->owner;
1068 host->rcdev.nr_resets = 1;
1069 err = devm_reset_controller_register(dev, &host->rcdev);
1074 host->generic_phy = devm_phy_get(dev, "ufsphy");
1075 if (IS_ERR(host->generic_phy)) {
1076 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1081 err = ufs_qcom_icc_init(host);
1085 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1087 if (IS_ERR(host->device_reset)) {
1088 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1093 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1094 &host->hw_ver.minor, &host->hw_ver.step);
1096 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1097 host->dev_ref_clk_en_mask = BIT(26);
1104 err = ufs_qcom_init_lane_clks(host);
1111 ufs_qcom_set_phy_gear(host);
1113 err = ufs_qcom_ice_init(host);
1119 ufs_qcom_get_default_testbus_cfg(host);
1120 err = ufs_qcom_testbus_config(host);
1136 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1138 ufs_qcom_disable_lane_clks(host);
1139 phy_power_off(host->generic_phy);
1140 phy_exit(host->generic_phy);
1146 * @hba: host controller instance
1155 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1161 * UFS host controller V4.0.0 onwards needs to program
1163 * frequency of unipro core clk of UFS host controller.
1165 if (host->hw_ver.major < 4)
1216 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1242 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1243 if (host->hw_ver.major >= 4) {
1270 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1271 struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1319 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1322 /* check the host controller state before sending hibern8 cmd */
1351 ufs_qcom_icc_update_bw(host);
1358 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1360 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1362 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1365 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1368 host->testbus.select_major = TSTBUS_UNIPRO;
1369 host->testbus.select_minor = 37;
1372 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1374 if (host->testbus.select_major >= TSTBUS_MAX) {
1375 dev_err(host->hba->dev,
1377 __func__, host->testbus.select_major);
1384 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1390 if (!host)
1393 if (!ufs_qcom_testbus_cfg_is_ok(host))
1396 switch (host->testbus.select_major) {
1453 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1454 (u32)host->testbus.select_major << 19,
1456 ufshcd_rmwl(host->hba, mask,
1457 (u32)host->testbus.select_minor << offset,
1459 ufs_qcom_enable_test_bus(host);
1467 struct ufs_qcom_host *host;
1469 host = ufshcd_get_variant(hba);
1474 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1481 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1484 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1487 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1493 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1496 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1499 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1502 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1505 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1508 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1511 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1523 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1526 if (!host->device_reset)
1562 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1564 phy_power_off(host->generic_phy);
1725 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1730 if (host->esi_enabled)
1770 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1771 host->hw_ver.step == 0)
1776 host->esi_enabled = true;