ufs/host/ufs-qcom.c

213 	int err;
215 	err = clk_bulk_prepare_enable(host->num_clks, host->clks);
216 	if (err)
217 		return err;
226 	int err;
232 	err = devm_clk_bulk_get_all(dev, &host->clks);
233 	if (err <= 0)
234 		return err;
236 	host->num_clks = err;
243 	int err;
248 		err = ufshcd_dme_get(hba,
252 		if (err || tx_fsm_val == TX_FSM_HIBERN8)
264 		err = ufshcd_dme_get(hba,
269 	if (err) {
270 		dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
271 				__func__, err);
273 		err = tx_fsm_val;
275 				__func__, err);
278 	return err;
306 		dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
320 		dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
422 	int err;
426 		err = ufs_qcom_power_up_sequence(hba);
427 		if (err)
428 			return err;
435 		err = ufs_qcom_enable_lane_clks(host);
439 		err = ufs_qcom_check_hibern8(hba);
445 		err = -EINVAL;
448 	return err;
516 	int err = 0;
527 		err = ufs_qcom_set_core_clk_ctrl(hba, true);
528 		if (err)
537 		err = ufshcd_disable_host_tx_lcc(hba);
544 	return err;
590 	int err;
593 		err = phy_power_on(phy);
594 		if (err) {
596 				__func__, err);
597 			return err;
600 		err = ufs_qcom_enable_lane_clks(host);
601 		if (err)
602 			return err;
605 		err = ufs_qcom_enable_lane_clks(host);
606 		if (err)
607 			return err;
811 	int err;
814 	err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
816 	if (err)
817 		return err;
826 	int err = 0;
829 		err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
834 	return err;
1043 	int err;
1059 		err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1069 	err = devm_reset_controller_register(dev, &host->rcdev);
1070 	if (err)
1076 			err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1081 	err = ufs_qcom_icc_init(host);
1082 	if (err)
1088 		err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1104 	err = ufs_qcom_init_lane_clks(host);
1105 	if (err)
1113 	err = ufs_qcom_ice_init(host);
1114 	if (err)
1120 	err = ufs_qcom_testbus_config(host);
1121 	if (err)
1124 				__func__, err);
1131 	return err;
1158 	int err;
1204 	err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), &reg);
1205 	if (err)
1206 		return err;
1221 	int err;
1236 	err = ufshcd_dme_get(hba,
1239 	if (err)
1240 		return err;
1258 	err = ufshcd_dme_set(hba,
1261 	if (err)
1262 		return err;
1291 	int err;
1294 	err = ufshcd_dme_get(hba,
1299 	if (!err &&
1302 		err = ufshcd_dme_set(hba,
1307 	return err;
1320 	int err;
1327 		err = ufshcd_uic_hibern8_enter(hba);
1328 		if (err)
1329 			return err;
1331 			err = ufs_qcom_clk_scale_up_pre_change(hba);
1333 			err = ufs_qcom_clk_scale_down_pre_change(hba);
1335 		if (err) {
1337 			return err;
1341 			err = ufs_qcom_clk_scale_up_post_change(hba);
1343 			err = ufs_qcom_clk_scale_down_post_change(hba);
1346 		if (err) {
1348 			return err;
1610 			dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1637 		dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1644 		dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1751 			dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1821 	int err;
1825 	err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1826 	if (err)
1827 		return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");