tty/serial/serial-tegra.c

151 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
152 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
153 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
156 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
159 	return readl(tup->uport.membase + (reg << tup->uport.regshift));
162 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
165 	writel(val, tup->uport.membase + (reg << tup->uport.regshift));
175 	struct tegra_uart_port *tup = to_tegra_uport(u);
186 	if (tup->enable_modem_interrupt)
191 static void set_rts(struct tegra_uart_port *tup, bool active)
195 	mcr = tup->mcr_shadow;
200 	if (mcr != tup->mcr_shadow) {
201 		tegra_uart_write(tup, mcr, UART_MCR);
202 		tup->mcr_shadow = mcr;
206 static void set_dtr(struct tegra_uart_port *tup, bool active)
210 	mcr = tup->mcr_shadow;
215 	if (mcr != tup->mcr_shadow) {
216 		tegra_uart_write(tup, mcr, UART_MCR);
217 		tup->mcr_shadow = mcr;
221 static void set_loopbk(struct tegra_uart_port *tup, bool active)
223 	unsigned long mcr = tup->mcr_shadow;
230 	if (mcr != tup->mcr_shadow) {
231 		tegra_uart_write(tup, mcr, UART_MCR);
232 		tup->mcr_shadow = mcr;
238 	struct tegra_uart_port *tup = to_tegra_uport(u);
241 	tup->rts_active = !!(mctrl & TIOCM_RTS);
242 	set_rts(tup, tup->rts_active);
245 	set_dtr(tup, enable);
248 	set_loopbk(tup, enable);
253 	struct tegra_uart_port *tup = to_tegra_uport(u);
256 	lcr = tup->lcr_shadow;
261 	tegra_uart_write(tup, lcr, UART_LCR);
262 	tup->lcr_shadow = lcr;
268  * @tup:	Tegra serial port data structure.
274 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
277 	if (tup->current_baud)
278 		udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
282 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
285 	if (tup->current_baud)
286 		udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
287 			tup->current_baud));
290 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
296 		iir = tegra_uart_read(tup, UART_IIR);
305 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
307 	unsigned long fcr = tup->fcr_shadow;
310 	if (tup->rts_active)
311 		set_rts(tup, false);
313 	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
315 		tegra_uart_write(tup, fcr, UART_FCR);
318 		tegra_uart_write(tup, fcr, UART_FCR);
321 		tegra_uart_write(tup, fcr, UART_FCR);
323 		tegra_uart_write(tup, fcr, UART_FCR);
324 		if (tup->cdata->fifo_mode_enable_status)
325 			tegra_uart_wait_fifo_mode_enabled(tup);
329 	tegra_uart_read(tup, UART_SCR);
336 	tegra_uart_wait_cycle_time(tup, 32);
339 		lsr = tegra_uart_read(tup, UART_LSR);
345 	if (tup->rts_active)
346 		set_rts(tup, true);
349 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
354 	for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
355 		if (baud >= tup->baud_tolerance[i].lower_range_baud &&
356 		    baud <= tup->baud_tolerance[i].upper_range_baud)
358 				tup->baud_tolerance[i].tolerance) / 10000);
364 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
368 	diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
369 		/ tup->required_rate;
370 	if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
371 	    diff > (tup->cdata->error_tolerance_high_range * 100)) {
372 		dev_err(tup->uport.dev,
380 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
388 	if (tup->current_baud == baud)
391 	if (tup->cdata->support_clk_src_div) {
393 		tup->required_rate = rate;
395 		if (tup->n_adjustable_baud_rates)
396 			rate = tegra_get_tolerance_rate(tup, baud, rate);
398 		ret = clk_set_rate(tup->uart_clk, rate);
400 			dev_err(tup->uport.dev,
404 		tup->configured_rate = clk_get_rate(tup->uart_clk);
406 		ret = tegra_check_rate_in_range(tup);
410 		rate = clk_get_rate(tup->uart_clk);
414 	uart_port_lock_irqsave(&tup->uport, &flags);
415 	lcr = tup->lcr_shadow;
417 	tegra_uart_write(tup, lcr, UART_LCR);
419 	tegra_uart_write(tup, divisor & 0xFF, UART_TX);
420 	tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
423 	tegra_uart_write(tup, lcr, UART_LCR);
426 	tegra_uart_read(tup, UART_SCR);
427 	uart_port_unlock_irqrestore(&tup->uport, flags);
429 	tup->current_baud = baud;
432 	tegra_uart_wait_sym_time(tup, 2);
436 static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
445 			tup->uport.icount.overrun++;
446 			dev_dbg(tup->uport.dev, "Got overrun errors\n");
450 			tup->uport.icount.parity++;
451 			dev_dbg(tup->uport.dev, "Got Parity errors\n");
454 			tup->uport.icount.frame++;
455 			dev_dbg(tup->uport.dev, "Got frame errors\n");
462 				tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
463 			if (tup->uport.ignore_status_mask & UART_LSR_BI)
466 			tup->uport.icount.brk++;
467 			dev_dbg(tup->uport.dev, "Got Break\n");
469 		uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
485 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
491 		if (tup->cdata->tx_fifo_full_status) {
492 			unsigned long lsr = tegra_uart_read(tup, UART_LSR);
496 		if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch)))
498 		tegra_uart_write(tup, ch, UART_TX);
502 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
508 	tup->tx_in_progress = TEGRA_UART_TX_PIO;
509 	tup->tx_bytes = bytes;
510 	tup->ier_shadow |= UART_IER_THRI;
511 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
516 	struct tegra_uart_port *tup = args;
517 	struct tty_port *tport = &tup->uport.state->port;
522 	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
523 	count = tup->tx_bytes_requested - state.residue;
524 	async_tx_ack(tup->tx_dma_desc);
525 	uart_port_lock_irqsave(&tup->uport, &flags);
526 	uart_xmit_advance(&tup->uport, count);
527 	tup->tx_in_progress = 0;
529 		uart_write_wakeup(&tup->uport);
530 	tegra_uart_start_next_tx(tup);
531 	uart_port_unlock_irqrestore(&tup->uport, flags);
534 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
537 	struct tty_port *tport = &tup->uport.state->port;
541 	tup->tx_bytes = count & ~(0xF);
544 	tx_phys_addr = tup->tx_dma_buf_phys + tail;
546 	dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
547 				   tup->tx_bytes, DMA_TO_DEVICE);
549 	tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
550 				tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
552 	if (!tup->tx_dma_desc) {
553 		dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
557 	tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
558 	tup->tx_dma_desc->callback_param = tup;
559 	tup->tx_in_progress = TEGRA_UART_TX_DMA;
560 	tup->tx_bytes_requested = tup->tx_bytes;
561 	tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
562 	dma_async_issue_pending(tup->tx_dma_chan);
566 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
568 	struct tty_port *tport = &tup->uport.state->port;
573 	if (!tup->current_baud)
583 	if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
584 		tegra_uart_start_pio_tx(tup, count);
586 		tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
588 		tegra_uart_start_tx_dma(tup, count);
594 	struct tegra_uart_port *tup = to_tegra_uport(u);
597 	if (!kfifo_is_empty(&tport->xmit_fifo) && !tup->tx_in_progress)
598 		tegra_uart_start_next_tx(tup);
603 	struct tegra_uart_port *tup = to_tegra_uport(u);
608 	if (!tup->tx_in_progress) {
609 		unsigned long lsr = tegra_uart_read(tup, UART_LSR);
619 	struct tegra_uart_port *tup = to_tegra_uport(u);
623 	if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
626 	dmaengine_pause(tup->tx_dma_chan);
627 	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
628 	dmaengine_terminate_all(tup->tx_dma_chan);
629 	count = tup->tx_bytes_requested - state.residue;
630 	async_tx_ack(tup->tx_dma_desc);
631 	uart_xmit_advance(&tup->uport, count);
632 	tup->tx_in_progress = 0;
635 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
637 	struct tty_port *tport = &tup->uport.state->port;
639 	tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
640 	tup->tx_in_progress = 0;
642 		uart_write_wakeup(&tup->uport);
643 	tegra_uart_start_next_tx(tup);
646 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
653 		lsr = tegra_uart_read(tup, UART_LSR);
657 		flag = tegra_uart_decode_rx_error(tup, lsr);
661 		ch = (unsigned char) tegra_uart_read(tup, UART_RX);
662 		tup->uport.icount.rx++;
664 		if (uart_handle_sysrq_char(&tup->uport, ch))
667 		if (tup->uport.ignore_status_mask & UART_LSR_DR)
674 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
684 	tup->uport.icount.rx += count;
686 	if (tup->uport.ignore_status_mask & UART_LSR_DR)
689 	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
692 			((unsigned char *)(tup->rx_dma_buf_virt)), count);
695 		dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
697 	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
701 static void do_handle_rx_pio(struct tegra_uart_port *tup)
703 	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
704 	struct tty_port *port = &tup->uport.state->port;
706 	tegra_uart_handle_rx_pio(tup, port);
713 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
716 	struct tty_port *port = &tup->uport.state->port;
719 	async_tx_ack(tup->rx_dma_desc);
720 	count = tup->rx_bytes_requested - residue;
723 	tegra_uart_copy_rx_to_tty(tup, port, count);
725 	do_handle_rx_pio(tup);
730 	struct tegra_uart_port *tup = args;
731 	struct uart_port *u = &tup->uport;
738 	status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
741 		dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
746 	if (tup->rts_active)
747 		set_rts(tup, false);
749 	tup->rx_dma_active = false;
750 	tegra_uart_rx_buffer_push(tup, 0);
751 	tegra_uart_start_rx_dma(tup);
754 	if (tup->rts_active)
755 		set_rts(tup, true);
761 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
765 	if (!tup->rx_dma_active) {
766 		do_handle_rx_pio(tup);
770 	dmaengine_pause(tup->rx_dma_chan);
771 	dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
772 	dmaengine_terminate_all(tup->rx_dma_chan);
774 	tegra_uart_rx_buffer_push(tup, state.residue);
775 	tup->rx_dma_active = false;
778 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
781 	if (tup->rts_active)
782 		set_rts(tup, false);
784 	tegra_uart_terminate_rx_dma(tup);
786 	if (tup->rts_active)
787 		set_rts(tup, true);
790 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
794 	if (tup->rx_dma_active)
797 	tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
798 				tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
800 	if (!tup->rx_dma_desc) {
801 		dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
805 	tup->rx_dma_active = true;
806 	tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
807 	tup->rx_dma_desc->callback_param = tup;
808 	tup->rx_bytes_requested = count;
809 	tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
810 	dma_async_issue_pending(tup->rx_dma_chan);
816 	struct tegra_uart_port *tup = to_tegra_uport(u);
819 	msr = tegra_uart_read(tup, UART_MSR);
824 		tup->uport.icount.rng++;
826 		tup->uport.icount.dsr++;
829 		uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
832 		uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
837 	struct tegra_uart_port *tup = data;
838 	struct uart_port *u = &tup->uport;
847 		iir = tegra_uart_read(tup, UART_IIR);
849 			if (!tup->use_rx_pio && is_rx_int) {
850 				tegra_uart_handle_rx_dma(tup);
851 				if (tup->rx_in_progress) {
852 					ier = tup->ier_shadow;
855 					tup->ier_shadow = ier;
856 					tegra_uart_write(tup, ier, UART_IER);
859 				tegra_uart_start_rx_dma(tup);
871 			tup->ier_shadow &= ~UART_IER_THRI;
872 			tegra_uart_write(tup, tup->ier_shadow, UART_IER);
873 			tegra_uart_handle_tx_pio(tup);
878 			if (!tup->use_rx_pio) {
879 				is_rx_int = tup->rx_in_progress;
881 				ier = tup->ier_shadow;
884 				tup->ier_shadow = ier;
885 				tegra_uart_write(tup, ier, UART_IER);
890 			if (!tup->use_rx_pio) {
891 				is_rx_start = tup->rx_in_progress;
892 				tup->ier_shadow  &= ~UART_IER_RDI;
893 				tegra_uart_write(tup, tup->ier_shadow,
896 				do_handle_rx_pio(tup);
901 			tegra_uart_decode_rx_error(tup,
902 					tegra_uart_read(tup, UART_LSR));
914 	struct tegra_uart_port *tup = to_tegra_uport(u);
915 	struct tty_port *port = &tup->uport.state->port;
918 	if (tup->rts_active)
919 		set_rts(tup, false);
921 	if (!tup->rx_in_progress)
924 	tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
926 	ier = tup->ier_shadow;
929 	tup->ier_shadow = ier;
930 	tegra_uart_write(tup, ier, UART_IER);
931 	tup->rx_in_progress = 0;
933 	if (!tup->use_rx_pio)
934 		tegra_uart_terminate_rx_dma(tup);
936 		tegra_uart_handle_rx_pio(tup, port);
939 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
942 	unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
943 	unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
950 	tegra_uart_write(tup, 0, UART_IER);
952 	lsr = tegra_uart_read(tup, UART_LSR);
954 		msr = tegra_uart_read(tup, UART_MSR);
955 		mcr = tegra_uart_read(tup, UART_MCR);
957 			dev_err(tup->uport.dev,
966 				msr = tegra_uart_read(tup, UART_MSR);
967 				mcr = tegra_uart_read(tup, UART_MCR);
970 					dev_err(tup->uport.dev,
974 			lsr = tegra_uart_read(tup, UART_LSR);
978 	uart_port_lock_irqsave(&tup->uport, &flags);
980 	tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
981 	tup->current_baud = 0;
982 	uart_port_unlock_irqrestore(&tup->uport, flags);
984 	tup->rx_in_progress = 0;
985 	tup->tx_in_progress = 0;
987 	if (!tup->use_rx_pio)
988 		tegra_uart_dma_channel_free(tup, true);
989 	if (!tup->use_tx_pio)
990 		tegra_uart_dma_channel_free(tup, false);
992 	clk_disable_unprepare(tup->uart_clk);
995 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
999 	tup->fcr_shadow = 0;
1000 	tup->mcr_shadow = 0;
1001 	tup->lcr_shadow = 0;
1002 	tup->ier_shadow = 0;
1003 	tup->current_baud = 0;
1005 	ret = clk_prepare_enable(tup->uart_clk);
1007 		dev_err(tup->uport.dev, "could not enable clk\n");
1012 	reset_control_assert(tup->rst);
1014 	reset_control_deassert(tup->rst);
1016 	tup->rx_in_progress = 0;
1017 	tup->tx_in_progress = 0;
1037 	tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1039 	if (tup->use_rx_pio) {
1040 		tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1042 		if (tup->cdata->max_dma_burst_bytes == 8)
1043 			tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1045 			tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1048 	tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1049 	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1052 	tegra_uart_read(tup, UART_SCR);
1054 	if (tup->cdata->fifo_mode_enable_status) {
1055 		ret = tegra_uart_wait_fifo_mode_enabled(tup);
1057 			clk_disable_unprepare(tup->uart_clk);
1058 			dev_err(tup->uport.dev,
1069 		tegra_uart_wait_cycle_time(tup, 3);
1077 	ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1079 		clk_disable_unprepare(tup->uart_clk);
1080 		dev_err(tup->uport.dev, "Failed to set baud rate\n");
1083 	if (!tup->use_rx_pio) {
1084 		tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1085 		tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1086 		tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1088 		tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1090 	tup->rx_in_progress = 1;
1106 	tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1112 	if (!tup->use_rx_pio)
1113 		tup->ier_shadow |= TEGRA_UART_IER_EORD;
1115 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1119 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1123 		dmaengine_terminate_all(tup->rx_dma_chan);
1124 		dma_release_channel(tup->rx_dma_chan);
1125 		dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1126 				tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1127 		tup->rx_dma_chan = NULL;
1128 		tup->rx_dma_buf_phys = 0;
1129 		tup->rx_dma_buf_virt = NULL;
1131 		dmaengine_terminate_all(tup->tx_dma_chan);
1132 		dma_release_channel(tup->tx_dma_chan);
1133 		dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1135 		tup->tx_dma_chan = NULL;
1136 		tup->tx_dma_buf_phys = 0;
1137 		tup->tx_dma_buf_virt = NULL;
1141 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1150 	dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1153 		dev_err(tup->uport.dev,
1159 		dma_buf = dma_alloc_coherent(tup->uport.dev,
1163 			dev_err(tup->uport.dev,
1168 		dma_sync_single_for_device(tup->uport.dev, dma_phys,
1171 		dma_sconfig.src_addr = tup->uport.mapbase;
1173 		dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1174 		tup->rx_dma_chan = dma_chan;
1175 		tup->rx_dma_buf_virt = dma_buf;
1176 		tup->rx_dma_buf_phys = dma_phys;
1178 		dma_buf = tup->uport.state->port.xmit_buf;
1179 		dma_phys = dma_map_single(tup->uport.dev,
1181 		if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1182 			dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1186 		dma_sconfig.dst_addr = tup->uport.mapbase;
1189 		tup->tx_dma_chan = dma_chan;
1190 		tup->tx_dma_buf_virt = dma_buf;
1191 		tup->tx_dma_buf_phys = dma_phys;
1196 		dev_err(tup->uport.dev,
1198 		tegra_uart_dma_channel_free(tup, dma_to_memory);
1207 	struct tegra_uart_port *tup = to_tegra_uport(u);
1210 	if (!tup->use_tx_pio) {
1211 		ret = tegra_uart_dma_channel_allocate(tup, false);
1219 	if (!tup->use_rx_pio) {
1220 		ret = tegra_uart_dma_channel_allocate(tup, true);
1228 	ret = tegra_uart_hw_init(tup);
1235 				dev_name(u->dev), tup);
1243 	/* tup->uart_clk is already enabled in tegra_uart_hw_init */
1244 	clk_disable_unprepare(tup->uart_clk);
1246 	if (!tup->use_rx_pio)
1247 		tegra_uart_dma_channel_free(tup, true);
1249 	if (!tup->use_tx_pio)
1250 		tegra_uart_dma_channel_free(tup, false);
1260 	struct tegra_uart_port *tup = to_tegra_uport(u);
1262 	tup->tx_bytes = 0;
1263 	if (tup->tx_dma_chan)
1264 		dmaengine_terminate_all(tup->tx_dma_chan);
1269 	struct tegra_uart_port *tup = to_tegra_uport(u);
1271 	tegra_uart_hw_deinit(tup);
1272 	free_irq(u->irq, tup);
1277 	struct tegra_uart_port *tup = to_tegra_uport(u);
1279 	if (tup->enable_modem_interrupt) {
1280 		tup->ier_shadow |= UART_IER_MSI;
1281 		tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1289 	struct tegra_uart_port *tup = to_tegra_uport(u);
1294 	struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1296 	int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1303 	if (tup->rts_active)
1304 		set_rts(tup, false);
1307 	tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1308 	tegra_uart_read(tup, UART_IER);
1309 	tegra_uart_write(tup, 0, UART_IER);
1310 	tegra_uart_read(tup, UART_IER);
1313 	lcr = tup->lcr_shadow;
1341 	tegra_uart_write(tup, lcr, UART_LCR);
1342 	tup->lcr_shadow = lcr;
1343 	tup->symb_bit = tty_get_frame_size(termios->c_cflag);
1350 	ret = tegra_set_baudrate(tup, baud);
1352 		dev_err(tup->uport.dev, "Failed to set baud rate\n");
1361 		tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1362 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1363 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1365 		if (tup->rts_active)
1366 			set_rts(tup, true);
1368 		tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1369 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1370 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1377 	tegra_uart_read(tup, UART_IER);
1380 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1381 	tegra_uart_read(tup, UART_IER);
1383 	tup->uport.ignore_status_mask = 0;
1386 		tup->uport.ignore_status_mask |= UART_LSR_DR;
1388 		tup->uport.ignore_status_mask |= UART_LSR_BI;
1425 	struct tegra_uart_port *tup)
1440 	tup->uport.line = port;
1442 	tup->enable_modem_interrupt = of_property_read_bool(np,
1447 		tup->use_rx_pio = true;
1452 		tup->use_tx_pio = true;
1458 		tup->n_adjustable_baud_rates = n_entries / 3;
1459 		tup->baud_tolerance =
1460 		devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1461 			     sizeof(*tup->baud_tolerance), GFP_KERNEL);
1462 		if (!tup->baud_tolerance)
1471 				tup->baud_tolerance[index].lower_range_baud =
1478 				tup->baud_tolerance[index].upper_range_baud =
1485 				tup->baud_tolerance[index].tolerance =
1489 		tup->n_adjustable_baud_rates = 0;
1559 	struct tegra_uart_port *tup;
1571 	tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1572 	if (!tup) {
1573 		dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1577 	ret = tegra_uart_parse_dt(pdev, tup);
1581 	u = &tup->uport;
1586 	tup->cdata = cdata;
1588 	platform_set_drvdata(pdev, tup);
1595 	tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1596 	if (IS_ERR(tup->uart_clk))
1597 		return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock");
1599 	tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1600 	if (IS_ERR(tup->rst)) {
1602 		return PTR_ERR(tup->rst);
1621 	struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1622 	struct uart_port *u = &tup->uport;
1630 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1631 	struct uart_port *u = &tup->uport;
1638 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1639 	struct uart_port *u = &tup->uport;