Lines Matching refs:ulcon
1477 u32 ulcon, umcon;
1529 ulcon = S3C2410_LCON_CS5;
1533 ulcon = S3C2410_LCON_CS6;
1537 ulcon = S3C2410_LCON_CS7;
1542 ulcon = S3C2410_LCON_CS8;
1547 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1550 ulcon |= S3C2410_LCON_STOPB;
1554 ulcon |= S3C2410_LCON_PODD;
1556 ulcon |= S3C2410_LCON_PEVEN;
1558 ulcon |= S3C2410_LCON_PNONE;
1564 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1565 ulcon, quot, udivslot);
1567 wr_regl(port, S3C2410_ULCON, ulcon);
1587 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
2292 u32 ulcon, ucon, ubrdiv;
2296 ulcon = rd_regl(port, S3C2410_ULCON);
2301 switch (ulcon & S3C2410_LCON_CSMASK) {
2317 switch (ulcon & S3C2410_LCON_PMASK) {