65 static void mlb_usio_stop_tx(struct uart_port *port)
67 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 	       port->membase + MLB_USIO_REG_FCR);
69 	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 	       port->membase + MLB_USIO_REG_SCR);
73 static void mlb_usio_tx_chars(struct uart_port *port)
75 	struct tty_port *tport = &port->state->port;
78 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 	       port->membase + MLB_USIO_REG_FCR);
80 	writeb(readb(port->membase + MLB_USIO_REG_SCR) &
82 	       port->membase + MLB_USIO_REG_SCR);
84 	if (port->x_char) {
85 		writew(port->x_char, port->membase + MLB_USIO_REG_DR);
86 		port->icount.tx++;
87 		port->x_char = 0;
90 	if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
91 		mlb_usio_stop_tx(port);
95 	count = port->fifosize -
96 		(readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
101 		if (!uart_fifo_get(port, &ch))
104 		writew(ch, port->membase + MLB_USIO_REG_DR);
105 		port->icount.tx++;
108 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
109 	       port->membase + MLB_USIO_REG_FCR);
111 	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
112 	       port->membase + MLB_USIO_REG_SCR);
115 		uart_write_wakeup(port);
118 		mlb_usio_stop_tx(port);
121 static void mlb_usio_start_tx(struct uart_port *port)
123 	u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
125 	writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
129 	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
130 	       port->membase + MLB_USIO_REG_SCR);
132 	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
133 		mlb_usio_tx_chars(port);
136 static void mlb_usio_stop_rx(struct uart_port *port)
138 	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
139 	       port->membase + MLB_USIO_REG_SCR);
142 static void mlb_usio_enable_ms(struct uart_port *port)
144 	writeb(readb(port->membase + MLB_USIO_REG_SCR) |
146 	       port->membase + MLB_USIO_REG_SCR);
149 static void mlb_usio_rx_chars(struct uart_port *port)
151 	struct tty_port *ttyport = &port->state->port;
157 		status = readb(port->membase + MLB_USIO_REG_SSR);
164 			ch = readw(port->membase + MLB_USIO_REG_DR);
166 			port->icount.rx++;
167 			if (uart_handle_sysrq_char(port, ch))
169 			uart_insert_char(port, status, MLB_USIO_SSR_ORE,
174 			port->icount.parity++;
176 			port->icount.overrun++;
177 		status &= port->read_status_mask;
191 			uart_insert_char(port, status, MLB_USIO_SSR_ORE,
194 		writeb(readb(port->membase + MLB_USIO_REG_SSR) |
196 				port->membase + MLB_USIO_REG_SSR);
198 		max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
199 		writew(readw(port->membase + MLB_USIO_REG_FCR) |
201 		port->membase + MLB_USIO_REG_FCR);
209 	struct uart_port *port = dev_id;
211 	uart_port_lock(port);
212 	mlb_usio_rx_chars(port);
213 	uart_port_unlock(port);
220 	struct uart_port *port = dev_id;
222 	uart_port_lock(port);
223 	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
224 		mlb_usio_tx_chars(port);
225 	uart_port_unlock(port);
230 static unsigned int mlb_usio_tx_empty(struct uart_port *port)
232 	return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
236 static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
240 static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
246 static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
250 static int mlb_usio_startup(struct uart_port *port)
252 	const char *portname = to_platform_device(port->dev)->name;
254 	int ret, index = port->line;
258 				0, portname, port);
262 				0, portname, port);
264 		free_irq(mlb_usio_irq[index][RX], port);
268 	escr = readb(port->membase + MLB_USIO_REG_ESCR);
269 	if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
271 	uart_port_lock_irqsave(port, &flags);
272 	writeb(0, port->membase + MLB_USIO_REG_SCR);
273 	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
274 	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
275 	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
276 	writew(0, port->membase + MLB_USIO_REG_FCR);
278 	       port->membase + MLB_USIO_REG_FCR);
280 	       port->membase + MLB_USIO_REG_FCR);
281 	writew(0, port->membase + MLB_USIO_REG_FBYTE);
282 	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
285 	       MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
286 	uart_port_unlock_irqrestore(port, flags);
291 static void mlb_usio_shutdown(struct uart_port *port)
293 	int index = port->line;
295 	free_irq(mlb_usio_irq[index][RX], port);
296 	free_irq(mlb_usio_irq[index][TX], port);
299 static void mlb_usio_set_termios(struct uart_port *port,
331 	if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
335 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
337 		quot = port->uartclk / baud - 1;
341 	uart_port_lock_irqsave(port, &flags);
342 	uart_update_timeout(port, termios->c_cflag, baud);
343 	port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
346 		port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
348 	port->ignore_status_mask = 0;
350 		port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
352 		port->ignore_status_mask |= MLB_USIO_SSR_ORE;
354 		port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
356 	writeb(0, port->membase + MLB_USIO_REG_SCR);
357 	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
358 	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
359 	writew(0, port->membase + MLB_USIO_REG_FCR);
360 	writeb(smr, port->membase + MLB_USIO_REG_SMR);
361 	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
362 	writew(quot, port->membase + MLB_USIO_REG_BGR);
363 	writew(0, port->membase + MLB_USIO_REG_FCR);
366 	       port->membase + MLB_USIO_REG_FCR);
367 	writew(0, port->membase + MLB_USIO_REG_FBYTE);
368 	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
370 	       MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
371 	uart_port_unlock_irqrestore(port, flags);
374 static const char *mlb_usio_type(struct uart_port *port)
376 	return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
379 static void mlb_usio_config_port(struct uart_port *port, int flags)
382 		port->type = PORT_MLB_USIO;
403 static void mlb_usio_console_putchar(struct uart_port *port, unsigned char c)
405 	while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
408 	writew(c, port->membase + MLB_USIO_REG_DR);
414 	struct uart_port *port = &mlb_usio_ports[co->index];
416 	uart_console_write(port, s, count, mlb_usio_console_putchar);
421 	struct uart_port *port;
430 	port = &mlb_usio_ports[co->index];
431 	if (!port->membase)
438 	if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
441 	return uart_set_options(port, co, baud, parity, bits, flow);
469 	uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
475 	if (!device->port.membase)
500 	struct uart_port *port;
515 	port = &mlb_usio_ports[index];
517 	port->private_data = (void *)clk;
524 	port->membase = devm_ioremap(&pdev->dev, res->start,
533 	port->irq = mlb_usio_irq[index][RX];
534 	port->uartclk = clk_get_rate(clk);
535 	port->fifosize = 128;
536 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE);
537 	port->iotype = UPIO_MEM32;
538 	port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
539 	port->line = index;
540 	port->ops = &mlb_usio_ops;
541 	port->dev = &pdev->dev;
543 	ret = uart_add_one_port(&mlb_usio_uart_driver, port);
545 		dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
558 	struct uart_port *port = &mlb_usio_ports[pdev->id];
559 	struct clk *clk = port->private_data;
561 	uart_remove_one_port(&mlb_usio_uart_driver, port);

Indexes created Sat May 25 20:21:57 MDT 2024