Lines Matching refs:AML_UART_CONTROL
26 #define AML_UART_CONTROL 0x08
31 /* AML_UART_CONTROL bits */
111 val = readl(port->membase + AML_UART_CONTROL);
113 writel(val, port->membase + AML_UART_CONTROL);
120 val = readl(port->membase + AML_UART_CONTROL);
122 writel(val, port->membase + AML_UART_CONTROL);
134 val = readl(port->membase + AML_UART_CONTROL);
137 writel(val, port->membase + AML_UART_CONTROL);
168 val = readl(port->membase + AML_UART_CONTROL);
170 writel(val, port->membase + AML_UART_CONTROL);
196 mode = readl(port->membase + AML_UART_CONTROL);
198 writel(mode, port->membase + AML_UART_CONTROL);
202 writel(mode, port->membase + AML_UART_CONTROL);
245 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
271 val = readl(port->membase + AML_UART_CONTROL);
273 writel(val, port->membase + AML_UART_CONTROL);
276 writel(val, port->membase + AML_UART_CONTROL);
287 val = readl(port->membase + AML_UART_CONTROL);
289 writel(val, port->membase + AML_UART_CONTROL);
291 writel(val, port->membase + AML_UART_CONTROL);
294 writel(val, port->membase + AML_UART_CONTROL);
297 writel(val, port->membase + AML_UART_CONTROL);
347 val = readl(port->membase + AML_UART_CONTROL);
390 writel(val, port->membase + AML_UART_CONTROL);
538 val = readl(port->membase + AML_UART_CONTROL);
540 writel(val, port->membase + AML_UART_CONTROL);
565 val = readl(port->membase + AML_UART_CONTROL);
567 writel(tmp, port->membase + AML_UART_CONTROL);
570 writel(val, port->membase + AML_UART_CONTROL);