Lines Matching refs:ch
35 static void neo_set_cts_flow_control(struct jsm_channel *ch)
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
51 writeb(0, &ch->ch_neo_uart->efr);
54 writeb(efr, &ch->ch_neo_uart->efr);
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
60 writeb(8, &ch->ch_neo_uart->tfifo);
61 ch->ch_t_tlevel = 8;
63 writeb(ier, &ch->ch_neo_uart->ier);
66 static void neo_set_rts_flow_control(struct jsm_channel *ch)
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
83 writeb(0, &ch->ch_neo_uart->efr);
86 writeb(efr, &ch->ch_neo_uart->efr);
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
91 writeb(56, &ch->ch_neo_uart->rfifo);
92 ch->ch_r_tlevel = 56;
94 writeb(ier, &ch->ch_neo_uart->ier);
102 ch->ch_mostat |= (UART_MCR_RTS);
106 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
122 writeb(0, &ch->ch_neo_uart->efr);
125 writeb(efr, &ch->ch_neo_uart->efr);
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
140 writeb(ier, &ch->ch_neo_uart->ier);
143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
160 writeb(0, &ch->ch_neo_uart->efr);
163 writeb(efr, &ch->ch_neo_uart->efr);
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
168 writeb(8, &ch->ch_neo_uart->tfifo);
169 ch->ch_t_tlevel = 8;
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
178 writeb(ier, &ch->ch_neo_uart->ier);
181 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
195 if (ch->ch_c_iflag & IXON)
201 writeb(0, &ch->ch_neo_uart->efr);
204 writeb(efr, &ch->ch_neo_uart->efr);
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
209 ch->ch_r_watermark = 0;
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
217 writeb(ier, &ch->ch_neo_uart->ier);
220 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
233 if (ch->ch_c_iflag & IXOFF)
239 writeb(0, &ch->ch_neo_uart->efr);
242 writeb(efr, &ch->ch_neo_uart->efr);
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
247 ch->ch_r_watermark = 0;
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
255 writeb(ier, &ch->ch_neo_uart->ier);
258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
262 if (ch->ch_c_cflag & CRTSCTS)
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
305 if (!(ch->ch_flags & CH_FIFO_ENABLED))
308 total = readb(&ch->ch_neo_uart->rfifo);
334 linestatus = readb(&ch->ch_neo_uart->lsr);
361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
372 memset(ch->ch_equeue + head, 0, n);
378 ch->ch_rxcount += n;
385 if (ch->ch_c_iflag & IGNBRK)
398 linestatus |= readb(&ch->ch_neo_uart->lsr);
406 ch->ch_cached_lsr = linestatus;
420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
442 jsm_dbg(READ, &ch->ch_bd->pci_dev,
444 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
447 ch->ch_err_overrun++;
451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
452 ch->ch_equeue[head] = (u8) linestatus;
454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
455 ch->ch_rqueue[head], ch->ch_equeue[head]);
464 ch->ch_rxcount++;
470 ch->ch_r_head = head & RQUEUEMASK;
471 ch->ch_e_head = head & EQUEUEMASK;
472 jsm_input(ch);
475 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
485 if (!ch)
488 circ = &ch->uart_port.state->xmit;
495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
503 ch->ch_cached_lsr |= lsrbits;
504 if (ch->ch_cached_lsr & UART_LSR_THRE) {
505 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
507 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
508 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
511 ch->ch_txcount++;
519 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
522 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
540 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
544 ch->ch_txcount += s;
551 if (len_written >= ch->ch_t_tlevel)
552 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
555 uart_write_wakeup(&ch->uart_port);
558 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
562 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
564 ch->ch_portnum, msignals);
571 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
573 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
575 ch->ch_mistat |= UART_MSR_DCD;
577 ch->ch_mistat &= ~UART_MSR_DCD;
580 ch->ch_mistat |= UART_MSR_DSR;
582 ch->ch_mistat &= ~UART_MSR_DSR;
585 ch->ch_mistat |= UART_MSR_RI;
587 ch->ch_mistat &= ~UART_MSR_RI;
590 ch->ch_mistat |= UART_MSR_CTS;
592 ch->ch_mistat &= ~UART_MSR_CTS;
594 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
596 ch->ch_portnum,
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
602 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
606 static void neo_assert_modem_signals(struct jsm_channel *ch)
608 if (!ch)
611 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
614 neo_pci_posting_flush(ch->ch_bd);
622 static void neo_flush_uart_write(struct jsm_channel *ch)
627 if (!ch)
630 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
635 tmp = readb(&ch->ch_neo_uart->isr_fcr);
637 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
645 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
654 static void neo_flush_uart_read(struct jsm_channel *ch)
659 if (!ch)
662 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
667 tmp = readb(&ch->ch_neo_uart->isr_fcr);
669 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
681 static void neo_clear_break(struct jsm_channel *ch)
685 spin_lock_irqsave(&ch->ch_lock, lock_flags);
688 if (ch->ch_flags & CH_BREAK_SENDING) {
689 u8 temp = readb(&ch->ch_neo_uart->lcr);
690 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
692 ch->ch_flags &= ~(CH_BREAK_SENDING);
693 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
698 neo_pci_posting_flush(ch->ch_bd);
700 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
708 struct jsm_channel *ch;
719 ch = brd->channels[port];
720 if (!ch)
726 isr = readb(&ch->ch_neo_uart->isr_fcr);
737 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
742 neo_copy_data_from_uart_to_queue(ch);
745 spin_lock_irqsave(&ch->ch_lock, lock_flags);
746 jsm_check_queue_flow_control(ch);
747 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
752 spin_lock_irqsave(&ch->ch_lock, lock_flags);
753 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
754 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
755 neo_copy_data_from_queue_to_uart(ch);
759 cause = readb(&ch->ch_neo_uart->xoffchar1);
761 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
770 spin_lock_irqsave(&ch->ch_lock, lock_flags);
774 ch->ch_flags &= ~(CH_STOP);
776 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
782 ch->ch_flags |= CH_STOP;
783 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
786 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
790 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
798 cause = readb(&ch->ch_neo_uart->mcr);
801 spin_lock_irqsave(&ch->ch_lock, lock_flags);
804 ch->ch_mostat |= UART_MCR_RTS;
806 ch->ch_mostat &= ~(UART_MCR_RTS);
809 ch->ch_mostat |= UART_MCR_DTR;
811 ch->ch_mostat &= ~(UART_MCR_DTR);
813 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
817 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
819 uart_port_lock_irqsave(&ch->uart_port, &lock_flags);
820 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
821 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags);
827 struct jsm_channel *ch;
837 ch = brd->channels[port];
838 if (!ch)
841 linestatus = readb(&ch->ch_neo_uart->lsr);
843 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
846 ch->ch_cached_lsr |= linestatus;
848 if (ch->ch_cached_lsr & UART_LSR_DR) {
850 neo_copy_data_from_uart_to_queue(ch);
851 spin_lock_irqsave(&ch->ch_lock, lock_flags);
852 jsm_check_queue_flow_control(ch);
853 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
863 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
873 ch->ch_err_parity++;
874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
879 ch->ch_err_frame++;
880 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
885 ch->ch_err_break++;
886 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
898 ch->ch_err_overrun++;
899 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
905 spin_lock_irqsave(&ch->ch_lock, lock_flags);
906 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
907 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
910 neo_copy_data_from_queue_to_uart(ch);
913 spin_lock_irqsave(&ch->ch_lock, lock_flags);
914 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
915 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
918 neo_copy_data_from_queue_to_uart(ch);
926 static void neo_param(struct jsm_channel *ch)
934 bd = ch->ch_bd;
941 if ((ch->ch_c_cflag & CBAUD) == B0) {
942 ch->ch_r_head = ch->ch_r_tail = 0;
943 ch->ch_e_head = ch->ch_e_tail = 0;
945 neo_flush_uart_write(ch);
946 neo_flush_uart_read(ch);
948 ch->ch_flags |= (CH_BAUD0);
949 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
950 neo_assert_modem_signals(ch);
981 cflag = C_BAUD(ch->uart_port.state->port.tty);
990 if (ch->ch_flags & CH_BAUD0)
991 ch->ch_flags &= ~(CH_BAUD0);
994 if (ch->ch_c_cflag & PARENB)
997 if (!(ch->ch_c_cflag & PARODD))
1000 if (ch->ch_c_cflag & CMSPAR)
1003 if (ch->ch_c_cflag & CSTOPB)
1006 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
1008 ier = readb(&ch->ch_neo_uart->ier);
1009 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1011 quot = ch->ch_bd->bd_dividend / baud;
1014 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1015 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1016 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1017 writeb(lcr, &ch->ch_neo_uart->lcr);
1021 writeb(lcr, &ch->ch_neo_uart->lcr);
1023 if (ch->ch_c_cflag & CREAD)
1028 writeb(ier, &ch->ch_neo_uart->ier);
1031 neo_set_new_start_stop_chars(ch);
1033 if (ch->ch_c_cflag & CRTSCTS)
1034 neo_set_cts_flow_control(ch);
1035 else if (ch->ch_c_iflag & IXON) {
1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1038 neo_set_no_output_flow_control(ch);
1040 neo_set_ixon_flow_control(ch);
1043 neo_set_no_output_flow_control(ch);
1045 if (ch->ch_c_cflag & CRTSCTS)
1046 neo_set_rts_flow_control(ch);
1047 else if (ch->ch_c_iflag & IXOFF) {
1049 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1050 neo_set_no_input_flow_control(ch);
1052 neo_set_ixoff_flow_control(ch);
1055 neo_set_no_input_flow_control(ch);
1062 writeb(1, &ch->ch_neo_uart->rfifo);
1063 ch->ch_r_tlevel = 1;
1066 neo_assert_modem_signals(ch);
1069 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1081 struct jsm_channel *ch;
1157 ch = brd->channels[port];
1158 if (!ch)
1161 neo_copy_data_from_uart_to_queue(ch);
1164 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1165 jsm_check_queue_flow_control(ch);
1166 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1225 static void neo_disable_receiver(struct jsm_channel *ch)
1227 u8 tmp = readb(&ch->ch_neo_uart->ier);
1229 writeb(tmp, &ch->ch_neo_uart->ier);
1232 neo_pci_posting_flush(ch->ch_bd);
1241 static void neo_enable_receiver(struct jsm_channel *ch)
1243 u8 tmp = readb(&ch->ch_neo_uart->ier);
1245 writeb(tmp, &ch->ch_neo_uart->ier);
1248 neo_pci_posting_flush(ch->ch_bd);
1251 static void neo_send_start_character(struct jsm_channel *ch)
1253 if (!ch)
1256 if (ch->ch_startc != __DISABLED_CHAR) {
1257 ch->ch_xon_sends++;
1258 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1261 neo_pci_posting_flush(ch->ch_bd);
1265 static void neo_send_stop_character(struct jsm_channel *ch)
1267 if (!ch)
1270 if (ch->ch_stopc != __DISABLED_CHAR) {
1271 ch->ch_xoff_sends++;
1272 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1275 neo_pci_posting_flush(ch->ch_bd);
1282 static void neo_uart_init(struct jsm_channel *ch)
1284 writeb(0, &ch->ch_neo_uart->ier);
1285 writeb(0, &ch->ch_neo_uart->efr);
1286 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1289 readb(&ch->ch_neo_uart->txrx);
1290 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1291 readb(&ch->ch_neo_uart->lsr);
1292 readb(&ch->ch_neo_uart->msr);
1294 ch->ch_flags |= CH_FIFO_ENABLED;
1297 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1303 static void neo_uart_off(struct jsm_channel *ch)
1306 writeb(0, &ch->ch_neo_uart->efr);
1309 writeb(0, &ch->ch_neo_uart->ier);
1313 static void neo_send_break(struct jsm_channel *ch)
1322 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1323 u8 temp = readb(&ch->ch_neo_uart->lcr);
1324 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1325 ch->ch_flags |= (CH_BREAK_SENDING);
1328 neo_pci_posting_flush(ch->ch_bd);