Lines Matching defs:ch
35 static void neo_set_cts_flow_control(struct jsm_channel *ch)
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
51 writeb(0, &ch->ch_neo_uart->efr);
54 writeb(efr, &ch->ch_neo_uart->efr);
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
60 writeb(8, &ch->ch_neo_uart->tfifo);
61 ch->ch_t_tlevel = 8;
63 writeb(ier, &ch->ch_neo_uart->ier);
66 static void neo_set_rts_flow_control(struct jsm_channel *ch)
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
83 writeb(0, &ch->ch_neo_uart->efr);
86 writeb(efr, &ch->ch_neo_uart->efr);
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
91 writeb(56, &ch->ch_neo_uart->rfifo);
92 ch->ch_r_tlevel = 56;
94 writeb(ier, &ch->ch_neo_uart->ier);
102 ch->ch_mostat |= (UART_MCR_RTS);
106 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
122 writeb(0, &ch->ch_neo_uart->efr);
125 writeb(efr, &ch->ch_neo_uart->efr);
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
140 writeb(ier, &ch->ch_neo_uart->ier);
143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
160 writeb(0, &ch->ch_neo_uart->efr);
163 writeb(efr, &ch->ch_neo_uart->efr);
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
168 writeb(8, &ch->ch_neo_uart->tfifo);
169 ch->ch_t_tlevel = 8;
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
178 writeb(ier, &ch->ch_neo_uart->ier);
181 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
195 if (ch->ch_c_iflag & IXON)
201 writeb(0, &ch->ch_neo_uart->efr);
204 writeb(efr, &ch->ch_neo_uart->efr);
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
209 ch->ch_r_watermark = 0;
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
217 writeb(ier, &ch->ch_neo_uart->ier);
220 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
233 if (ch->ch_c_iflag & IXOFF)
239 writeb(0, &ch->ch_neo_uart->efr);
242 writeb(efr, &ch->ch_neo_uart->efr);
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
247 ch->ch_r_watermark = 0;
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
255 writeb(ier, &ch->ch_neo_uart->ier);
258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
262 if (ch->ch_c_cflag & CRTSCTS)
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
305 if (!(ch->ch_flags & CH_FIFO_ENABLED))
308 total = readb(&ch->ch_neo_uart->rfifo);
334 linestatus = readb(&ch->ch_neo_uart->lsr);
361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
372 memset(ch->ch_equeue + head, 0, n);
378 ch->ch_rxcount += n;
385 if (ch->ch_c_iflag & IGNBRK)
398 linestatus |= readb(&ch->ch_neo_uart->lsr);
406 ch->ch_cached_lsr = linestatus;
420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
442 jsm_dbg(READ, &ch->ch_bd->pci_dev,
444 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
447 ch->ch_err_overrun++;
451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
452 ch->ch_equeue[head] = (u8) linestatus;
454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
455 ch->ch_rqueue[head], ch->ch_equeue[head]);
464 ch->ch_rxcount++;
470 ch->ch_r_head = head & RQUEUEMASK;
471 ch->ch_e_head = head & EQUEUEMASK;
472 jsm_input(ch);
475 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
485 if (!ch)
488 tport = &ch->uart_port.state->port;
495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
503 ch->ch_cached_lsr |= lsrbits;
504 if (ch->ch_cached_lsr & UART_LSR_THRE) {
505 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
508 writeb(c, &ch->ch_neo_uart->txrx);
509 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, "Tx data: %x\n", c);
510 ch->ch_txcount++;
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
532 memcpy_toio(&ch->ch_neo_uart->txrxburst, tail, s);
535 ch->ch_txcount += s;
539 if (len_written >= ch->ch_t_tlevel)
540 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
543 uart_write_wakeup(&ch->uart_port);
546 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
550 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
552 ch->ch_portnum, msignals);
559 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
561 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
563 ch->ch_mistat |= UART_MSR_DCD;
565 ch->ch_mistat &= ~UART_MSR_DCD;
568 ch->ch_mistat |= UART_MSR_DSR;
570 ch->ch_mistat &= ~UART_MSR_DSR;
573 ch->ch_mistat |= UART_MSR_RI;
575 ch->ch_mistat &= ~UART_MSR_RI;
578 ch->ch_mistat |= UART_MSR_CTS;
580 ch->ch_mistat &= ~UART_MSR_CTS;
582 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
584 ch->ch_portnum,
585 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
586 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
587 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
588 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
589 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
590 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
594 static void neo_assert_modem_signals(struct jsm_channel *ch)
596 if (!ch)
599 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
602 neo_pci_posting_flush(ch->ch_bd);
610 static void neo_flush_uart_write(struct jsm_channel *ch)
615 if (!ch)
618 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
623 tmp = readb(&ch->ch_neo_uart->isr_fcr);
625 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
633 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
642 static void neo_flush_uart_read(struct jsm_channel *ch)
647 if (!ch)
650 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
655 tmp = readb(&ch->ch_neo_uart->isr_fcr);
657 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
669 static void neo_clear_break(struct jsm_channel *ch)
673 spin_lock_irqsave(&ch->ch_lock, lock_flags);
676 if (ch->ch_flags & CH_BREAK_SENDING) {
677 u8 temp = readb(&ch->ch_neo_uart->lcr);
678 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
680 ch->ch_flags &= ~(CH_BREAK_SENDING);
681 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
686 neo_pci_posting_flush(ch->ch_bd);
688 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
696 struct jsm_channel *ch;
707 ch = brd->channels[port];
708 if (!ch)
714 isr = readb(&ch->ch_neo_uart->isr_fcr);
725 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
730 neo_copy_data_from_uart_to_queue(ch);
733 spin_lock_irqsave(&ch->ch_lock, lock_flags);
734 jsm_check_queue_flow_control(ch);
735 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
740 spin_lock_irqsave(&ch->ch_lock, lock_flags);
741 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
742 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
743 neo_copy_data_from_queue_to_uart(ch);
747 cause = readb(&ch->ch_neo_uart->xoffchar1);
749 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
758 spin_lock_irqsave(&ch->ch_lock, lock_flags);
762 ch->ch_flags &= ~(CH_STOP);
764 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
770 ch->ch_flags |= CH_STOP;
771 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
774 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
778 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
786 cause = readb(&ch->ch_neo_uart->mcr);
789 spin_lock_irqsave(&ch->ch_lock, lock_flags);
792 ch->ch_mostat |= UART_MCR_RTS;
794 ch->ch_mostat &= ~(UART_MCR_RTS);
797 ch->ch_mostat |= UART_MCR_DTR;
799 ch->ch_mostat &= ~(UART_MCR_DTR);
801 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
805 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
807 uart_port_lock_irqsave(&ch->uart_port, &lock_flags);
808 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
809 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags);
815 struct jsm_channel *ch;
825 ch = brd->channels[port];
826 if (!ch)
829 linestatus = readb(&ch->ch_neo_uart->lsr);
831 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
834 ch->ch_cached_lsr |= linestatus;
836 if (ch->ch_cached_lsr & UART_LSR_DR) {
838 neo_copy_data_from_uart_to_queue(ch);
839 spin_lock_irqsave(&ch->ch_lock, lock_flags);
840 jsm_check_queue_flow_control(ch);
841 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
851 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
861 ch->ch_err_parity++;
862 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
867 ch->ch_err_frame++;
868 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
873 ch->ch_err_break++;
874 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
886 ch->ch_err_overrun++;
887 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
893 spin_lock_irqsave(&ch->ch_lock, lock_flags);
894 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
895 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
898 neo_copy_data_from_queue_to_uart(ch);
901 spin_lock_irqsave(&ch->ch_lock, lock_flags);
902 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
903 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
906 neo_copy_data_from_queue_to_uart(ch);
914 static void neo_param(struct jsm_channel *ch)
922 bd = ch->ch_bd;
929 if ((ch->ch_c_cflag & CBAUD) == B0) {
930 ch->ch_r_head = ch->ch_r_tail = 0;
931 ch->ch_e_head = ch->ch_e_tail = 0;
933 neo_flush_uart_write(ch);
934 neo_flush_uart_read(ch);
936 ch->ch_flags |= (CH_BAUD0);
937 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
938 neo_assert_modem_signals(ch);
969 cflag = C_BAUD(ch->uart_port.state->port.tty);
978 if (ch->ch_flags & CH_BAUD0)
979 ch->ch_flags &= ~(CH_BAUD0);
982 if (ch->ch_c_cflag & PARENB)
985 if (!(ch->ch_c_cflag & PARODD))
988 if (ch->ch_c_cflag & CMSPAR)
991 if (ch->ch_c_cflag & CSTOPB)
994 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
996 ier = readb(&ch->ch_neo_uart->ier);
997 uart_lcr = readb(&ch->ch_neo_uart->lcr);
999 quot = ch->ch_bd->bd_dividend / baud;
1002 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1003 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1004 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1005 writeb(lcr, &ch->ch_neo_uart->lcr);
1009 writeb(lcr, &ch->ch_neo_uart->lcr);
1011 if (ch->ch_c_cflag & CREAD)
1016 writeb(ier, &ch->ch_neo_uart->ier);
1019 neo_set_new_start_stop_chars(ch);
1021 if (ch->ch_c_cflag & CRTSCTS)
1022 neo_set_cts_flow_control(ch);
1023 else if (ch->ch_c_iflag & IXON) {
1025 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1026 neo_set_no_output_flow_control(ch);
1028 neo_set_ixon_flow_control(ch);
1031 neo_set_no_output_flow_control(ch);
1033 if (ch->ch_c_cflag & CRTSCTS)
1034 neo_set_rts_flow_control(ch);
1035 else if (ch->ch_c_iflag & IXOFF) {
1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1038 neo_set_no_input_flow_control(ch);
1040 neo_set_ixoff_flow_control(ch);
1043 neo_set_no_input_flow_control(ch);
1050 writeb(1, &ch->ch_neo_uart->rfifo);
1051 ch->ch_r_tlevel = 1;
1054 neo_assert_modem_signals(ch);
1057 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1069 struct jsm_channel *ch;
1145 ch = brd->channels[port];
1146 if (!ch)
1149 neo_copy_data_from_uart_to_queue(ch);
1152 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1153 jsm_check_queue_flow_control(ch);
1154 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1213 static void neo_disable_receiver(struct jsm_channel *ch)
1215 u8 tmp = readb(&ch->ch_neo_uart->ier);
1217 writeb(tmp, &ch->ch_neo_uart->ier);
1220 neo_pci_posting_flush(ch->ch_bd);
1229 static void neo_enable_receiver(struct jsm_channel *ch)
1231 u8 tmp = readb(&ch->ch_neo_uart->ier);
1233 writeb(tmp, &ch->ch_neo_uart->ier);
1236 neo_pci_posting_flush(ch->ch_bd);
1239 static void neo_send_start_character(struct jsm_channel *ch)
1241 if (!ch)
1244 if (ch->ch_startc != __DISABLED_CHAR) {
1245 ch->ch_xon_sends++;
1246 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1249 neo_pci_posting_flush(ch->ch_bd);
1253 static void neo_send_stop_character(struct jsm_channel *ch)
1255 if (!ch)
1258 if (ch->ch_stopc != __DISABLED_CHAR) {
1259 ch->ch_xoff_sends++;
1260 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1263 neo_pci_posting_flush(ch->ch_bd);
1270 static void neo_uart_init(struct jsm_channel *ch)
1272 writeb(0, &ch->ch_neo_uart->ier);
1273 writeb(0, &ch->ch_neo_uart->efr);
1274 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1277 readb(&ch->ch_neo_uart->txrx);
1278 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1279 readb(&ch->ch_neo_uart->lsr);
1280 readb(&ch->ch_neo_uart->msr);
1282 ch->ch_flags |= CH_FIFO_ENABLED;
1285 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1291 static void neo_uart_off(struct jsm_channel *ch)
1294 writeb(0, &ch->ch_neo_uart->efr);
1297 writeb(0, &ch->ch_neo_uart->ier);
1301 static void neo_send_break(struct jsm_channel *ch)
1310 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1311 u8 temp = readb(&ch->ch_neo_uart->lcr);
1312 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1313 ch->ch_flags |= (CH_BREAK_SENDING);
1316 neo_pci_posting_flush(ch->ch_bd);