tty/serial/ip22zilog.c

51 #define ZS_WSYNC(channel)	do { } while (0)
109 static unsigned char read_zsreg(struct zilog_channel *channel,
114 	writeb(reg, &channel->control);
116 	retval = readb(&channel->control);
122 static void write_zsreg(struct zilog_channel *channel,
125 	writeb(reg, &channel->control);
127 	writeb(value, &channel->control);
131 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
138 		regval = readb(&channel->control);
143 		regval = read_zsreg(channel, R1);
144 		readb(&channel->data);
148 			writeb(ERR_RES, &channel->control);
150 			ZS_WSYNC(channel);
158 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
164 		unsigned char stat = read_zsreg(channel, R1);
170 	writeb(ERR_RES, &channel->control);
172 	ZS_WSYNC(channel);
174 	ip22zilog_clear_fifo(channel);
177 	write_zsreg(channel, R1,
181 	write_zsreg(channel, R4, regs[R4]);
184 	write_zsreg(channel, R10, regs[R10]);
187 	write_zsreg(channel, R3, regs[R3] & ~RxENAB);
188 	write_zsreg(channel, R5, regs[R5] & ~TxENAB);
191 	write_zsreg(channel, R6, regs[R6]);
192 	write_zsreg(channel, R7, regs[R7]);
200 	write_zsreg(channel, R14, regs[R14] & ~BRENAB);
203 	write_zsreg(channel, R11, regs[R11]);
206 	write_zsreg(channel, R12, regs[R12]);
207 	write_zsreg(channel, R13, regs[R13]);
210 	write_zsreg(channel, R14, regs[R14]);
213 	write_zsreg(channel, R15, regs[R15]);
216 	write_zsreg(channel, R0, RES_EXT_INT);
217 	write_zsreg(channel, R0, RES_EXT_INT);
220 	write_zsreg(channel, R3, regs[R3]);
221 	write_zsreg(channel, R5, regs[R5]);
224 	write_zsreg(channel, R1, regs[R1]);
227 /* Reprogram the Zilog channel HW registers with the copies found in the
234 				       struct zilog_channel *channel)
240 			__load_zsregs(channel, up->curregs);
249 						  struct zilog_channel *channel)
256 		ch = readb(&channel->control);
261 		r1 = read_zsreg(channel, R1);
263 			writeb(ERR_RES, &channel->control);
265 			ZS_WSYNC(channel);
268 		ch = readb(&channel->data);
314 				   struct zilog_channel *channel)
318 	status = readb(&channel->control);
321 	writeb(RES_EXT_INT, &channel->control);
323 	ZS_WSYNC(channel);
356 				    struct zilog_channel *channel)
361 		unsigned char status = readb(&channel->control);
379 		__load_zsregs(channel, up->curregs);
390 		writeb(up->port.x_char, &channel->data);
392 		ZS_WSYNC(channel);
408 	writeb(xmit->buf[xmit->tail], &channel->data);
410 	ZS_WSYNC(channel);
420 	writeb(RES_Tx_P, &channel->control);
422 	ZS_WSYNC(channel);
430 		struct zilog_channel *channel
436 		r3 = read_zsreg(channel, R3);
440 			writeb(RES_H_IUS, &channel->control);
442 			ZS_WSYNC(channel);
445 				push = ip22zilog_receive_chars(up, channel);
447 				ip22zilog_status_handle(up, channel);
449 				ip22zilog_transmit_chars(up, channel);
458 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
463 			writeb(RES_H_IUS, &channel->control);
465 			ZS_WSYNC(channel);
468 				push = ip22zilog_receive_chars(up, channel);
470 				ip22zilog_status_handle(up, channel);
472 				ip22zilog_transmit_chars(up, channel);
490 	struct zilog_channel *channel;
493 	channel = ZILOG_CHANNEL_FROM_PORT(port);
494 	status = readb(&channel->control);
545 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
562 	write_zsreg(channel, R5, up->curregs[R5]);
579 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
585 	status = readb(&channel->control);
596 		writeb(port->x_char, &channel->data);
598 		ZS_WSYNC(channel);
607 		writeb(xmit->buf[xmit->tail], &channel->data);
609 		ZS_WSYNC(channel);
622 	struct zilog_channel *channel;
627 	channel = ZILOG_CHANNEL_FROM_PORT(port);
631 	ip22zilog_maybe_update_regs(up, channel);
639 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
647 		write_zsreg(channel, R15, up->curregs[R15]);
656 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
674 		write_zsreg(channel, R5, up->curregs[R5]);
682 	struct zilog_channel *channel;
689 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
691 		unsigned char stat = read_zsreg(channel, R1);
699 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
701 	write_zsreg(channel, R9, FHWRES);
703 	(void) read_zsreg(channel, R0);
711 	struct zilog_channel *channel;
713 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
717 	__load_zsregs(channel, up->curregs);
719 	write_zsreg(channel, R9, up->curregs[R9]);
720 	up->prev_status = readb(&channel->control);
727 	ip22zilog_maybe_update_regs(up, channel);
772 	struct zilog_channel *channel;
780 	channel = ZILOG_CHANNEL_FROM_PORT(port);
789 	ip22zilog_maybe_update_regs(up, channel);
993 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1000 		unsigned char val = readb(&channel->control);
1008 	writeb(ch, &channel->data);
1010 	ZS_WSYNC(channel);
1080 	int channel, chip;
1085 	for (channel = 0; channel < NUM_CHANNELS; channel++)
1086 		spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1090 	for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1091 		up[channel].next = &up[channel - 1];
1092 	up[channel].next = NULL;
1132 	for (channel = 0; channel < NUM_CHANNELS; channel++) {
1133 		struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];