Lines Matching refs:sport
361 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
363 return (sport->devtype == LS1021A_LPUART ||
364 sport->devtype == LS1028A_LPUART);
367 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
369 return sport->devtype == IMX7ULP_LPUART;
372 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
374 return sport->devtype == IMX8ULP_LPUART;
377 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
379 return sport->devtype == IMX8QXP_LPUART;
407 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
412 ret = clk_prepare_enable(sport->ipg_clk);
416 ret = clk_prepare_enable(sport->baud_clk);
418 clk_disable_unprepare(sport->ipg_clk);
422 clk_disable_unprepare(sport->baud_clk);
423 clk_disable_unprepare(sport->ipg_clk);
429 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
431 if (is_imx8qxp_lpuart(sport))
432 return clk_get_rate(sport->baud_clk);
434 return clk_get_rate(sport->ipg_clk);
474 static void lpuart_dma_tx(struct lpuart_port *sport)
476 struct circ_buf *xmit = &sport->port.state->xmit;
477 struct scatterlist *sgl = sport->tx_sgl;
478 struct device *dev = sport->port.dev;
479 struct dma_chan *chan = sport->dma_tx_chan;
482 if (sport->dma_tx_in_progress)
485 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
488 sport->dma_tx_nents = 1;
489 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
491 sport->dma_tx_nents = 2;
498 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
505 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
508 if (!sport->dma_tx_desc) {
509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
515 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
516 sport->dma_tx_desc->callback_param = sport;
517 sport->dma_tx_in_progress = true;
518 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
529 struct lpuart_port *sport = arg;
530 struct scatterlist *sgl = &sport->tx_sgl[0];
531 struct circ_buf *xmit = &sport->port.state->xmit;
532 struct dma_chan *chan = sport->dma_tx_chan;
535 uart_port_lock_irqsave(&sport->port, &flags);
536 if (!sport->dma_tx_in_progress) {
537 uart_port_unlock_irqrestore(&sport->port, flags);
541 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
544 uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
545 sport->dma_tx_in_progress = false;
546 uart_port_unlock_irqrestore(&sport->port, flags);
549 uart_write_wakeup(&sport->port);
551 if (waitqueue_active(&sport->dma_wait)) {
552 wake_up(&sport->dma_wait);
556 uart_port_lock_irqsave(&sport->port, &flags);
558 if (!lpuart_stopped_or_empty(&sport->port))
559 lpuart_dma_tx(sport);
561 uart_port_unlock_irqrestore(&sport->port, flags);
564 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
566 switch (sport->port.iotype) {
568 return sport->port.mapbase + UARTDATA;
570 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
572 return sport->port.mapbase + UARTDR;
577 struct lpuart_port *sport = container_of(port,
582 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
586 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
589 dev_err(sport->port.dev,
597 static bool lpuart_is_32(struct lpuart_port *sport)
599 return sport->port.iotype == UPIO_MEM32 ||
600 sport->port.iotype == UPIO_MEM32BE;
605 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
606 struct dma_chan *chan = sport->dma_tx_chan;
609 if (sport->lpuart_dma_tx_use) {
610 if (sport->dma_tx_in_progress) {
611 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
612 sport->dma_tx_nents, DMA_TO_DEVICE);
613 sport->dma_tx_in_progress = false;
618 if (lpuart_is_32(sport)) {
619 val = lpuart32_read(&sport->port, UARTFIFO);
621 lpuart32_write(&sport->port, val, UARTFIFO);
623 val = readb(sport->port.membase + UARTCFIFO);
625 writeb(val, sport->port.membase + UARTCFIFO);
647 struct lpuart_port *sport = container_of(port,
652 sport->port.fifosize = 0;
654 uart_port_lock_irqsave(&sport->port, &flags);
656 writeb(0, sport->port.membase + UARTCR2);
658 temp = readb(sport->port.membase + UARTPFIFO);
661 sport->port.membase + UARTPFIFO);
665 sport->port.membase + UARTCFIFO);
668 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
669 readb(sport->port.membase + UARTDR);
670 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
673 writeb(0, sport->port.membase + UARTTWFIFO);
674 writeb(1, sport->port.membase + UARTRWFIFO);
677 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
678 uart_port_unlock_irqrestore(&sport->port, flags);
701 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
704 sport->port.fifosize = 0;
706 uart_port_lock_irqsave(&sport->port, &flags);
709 lpuart32_write(&sport->port, 0, UARTCTRL);
711 temp = lpuart32_read(&sport->port, UARTFIFO);
714 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
717 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
720 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
721 lpuart32_read(&sport->port, UARTDATA);
722 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
726 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
727 uart_port_unlock_irqrestore(&sport->port, flags);
747 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
749 struct uart_port *port = &sport->port;
753 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
757 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
759 struct circ_buf *xmit = &sport->port.state->xmit;
762 if (sport->port.x_char) {
763 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
764 sport->port.icount.tx++;
765 sport->port.x_char = 0;
769 if (lpuart_stopped_or_empty(&sport->port)) {
770 lpuart32_stop_tx(&sport->port);
774 txcnt = lpuart32_read(&sport->port, UARTWATER);
777 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
778 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
779 uart_xmit_advance(&sport->port, 1);
780 txcnt = lpuart32_read(&sport->port, UARTWATER);
786 uart_write_wakeup(&sport->port);
789 lpuart32_stop_tx(&sport->port);
794 struct lpuart_port *sport = container_of(port,
801 if (sport->lpuart_dma_tx_use) {
803 lpuart_dma_tx(sport);
806 lpuart_transmit_buffer(sport);
812 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
815 if (sport->lpuart_dma_tx_use) {
817 lpuart_dma_tx(sport);
823 lpuart32_transmit_buffer(sport);
844 struct lpuart_port *sport = container_of(port,
849 if (sport->dma_tx_in_progress)
860 struct lpuart_port *sport = container_of(port,
866 if (sport->dma_tx_in_progress)
880 static void lpuart_txint(struct lpuart_port *sport)
882 uart_port_lock(&sport->port);
883 lpuart_transmit_buffer(sport);
884 uart_port_unlock(&sport->port);
887 static void lpuart_rxint(struct lpuart_port *sport)
890 struct tty_port *port = &sport->port.state->port;
893 uart_port_lock(&sport->port);
895 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
897 sport->port.icount.rx++;
902 sr = readb(sport->port.membase + UARTSR1);
903 rx = readb(sport->port.membase + UARTDR);
905 if (uart_prepare_sysrq_char(&sport->port, rx))
910 sport->port.icount.parity++;
912 sport->port.icount.frame++;
917 if (sr & sport->port.ignore_status_mask) {
923 sr &= sport->port.read_status_mask;
933 sport->port.sysrq = 0;
937 sport->port.icount.buf_overrun++;
942 sport->port.icount.overrun += overrun;
948 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
949 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
952 uart_unlock_and_check_sysrq(&sport->port);
957 static void lpuart32_txint(struct lpuart_port *sport)
959 uart_port_lock(&sport->port);
960 lpuart32_transmit_buffer(sport);
961 uart_port_unlock(&sport->port);
964 static void lpuart32_rxint(struct lpuart_port *sport)
967 struct tty_port *port = &sport->port.state->port;
971 uart_port_lock(&sport->port);
973 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
975 sport->port.icount.rx++;
980 sr = lpuart32_read(&sport->port, UARTSTAT);
981 rx = lpuart32_read(&sport->port, UARTDATA);
990 if (is_break && uart_handle_break(&sport->port))
993 if (uart_prepare_sysrq_char(&sport->port, rx))
998 sport->port.icount.parity++;
1001 sport->port.icount.brk++;
1003 sport->port.icount.frame++;
1007 sport->port.icount.overrun++;
1009 if (sr & sport->port.ignore_status_mask) {
1015 sr &= sport->port.read_status_mask;
1030 if (sport->is_cs7)
1034 sport->port.icount.buf_overrun++;
1038 uart_unlock_and_check_sysrq(&sport->port);
1045 struct lpuart_port *sport = dev_id;
1048 sts = readb(sport->port.membase + UARTSR1);
1051 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1052 readb(sport->port.membase + UARTDR);
1053 uart_handle_break(&sport->port);
1055 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1059 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1060 lpuart_rxint(sport);
1062 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1063 lpuart_txint(sport);
1078 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1080 struct circ_buf *ring = &sport->rx_ring;
1084 count = sport->rx_sgl.length - ring->tail;
1085 lpuart_handle_sysrq_chars(&sport->port,
1092 lpuart_handle_sysrq_chars(&sport->port,
1109 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1111 struct tty_port *port = &sport->port.state->port;
1114 struct dma_chan *chan = sport->dma_rx_chan;
1115 struct circ_buf *ring = &sport->rx_ring;
1119 if (lpuart_is_32(sport)) {
1120 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1124 lpuart32_write(&sport->port, sr, UARTSTAT);
1127 sport->port.icount.parity++;
1129 sport->port.icount.frame++;
1132 unsigned char sr = readb(sport->port.membase + UARTSR1);
1138 cr2 = readb(sport->port.membase + UARTCR2);
1140 writeb(cr2, sport->port.membase + UARTCR2);
1143 readb(sport->port.membase + UARTDR);
1146 sport->port.icount.parity++;
1148 sport->port.icount.frame++;
1158 if (readb(sport->port.membase + UARTSFIFO) &
1161 sport->port.membase + UARTSFIFO);
1163 sport->port.membase + UARTCFIFO);
1167 writeb(cr2, sport->port.membase + UARTCR2);
1171 async_tx_ack(sport->dma_rx_desc);
1173 uart_port_lock_irqsave(&sport->port, &flags);
1175 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1177 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1178 uart_port_unlock_irqrestore(&sport->port, flags);
1183 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1193 ring->head = sport->rx_sgl.length - state.residue;
1194 BUG_ON(ring->head > sport->rx_sgl.length);
1199 if (sport->port.sysrq) {
1200 lpuart_handle_sysrq(sport);
1207 * 0 <= ring->head <= sport->rx_sgl.length
1210 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1217 count = sport->rx_sgl.length - ring->tail;
1220 count, sport->is_cs7);
1222 sport->port.icount.buf_overrun++;
1224 sport->port.icount.rx += copied;
1231 count, sport->is_cs7);
1233 sport->port.icount.buf_overrun++;
1235 if (ring->head >= sport->rx_sgl.length)
1238 sport->port.icount.rx += copied;
1241 sport->last_residue = state.residue;
1244 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1247 uart_port_unlock_irqrestore(&sport->port, flags);
1250 if (!sport->dma_idle_int)
1251 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1256 struct lpuart_port *sport = arg;
1258 lpuart_copy_rx_to_tty(sport);
1261 static void lpuart32_dma_idleint(struct lpuart_port *sport)
1264 struct dma_chan *chan = sport->dma_rx_chan;
1265 struct circ_buf *ring = &sport->rx_ring;
1269 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1271 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1275 ring->head = sport->rx_sgl.length - state.residue;
1276 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1280 lpuart_copy_rx_to_tty(sport);
1285 struct lpuart_port *sport = dev_id;
1288 sts = lpuart32_read(&sport->port, UARTSTAT);
1289 rxcount = lpuart32_read(&sport->port, UARTWATER);
1292 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1293 lpuart32_rxint(sport);
1295 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1296 lpuart32_txint(sport);
1298 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int)
1299 lpuart32_dma_idleint(sport);
1301 lpuart32_write(&sport->port, sts, UARTSTAT);
1314 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1316 struct dma_chan *chan = sport->dma_rx_chan;
1317 struct circ_buf *ring = &sport->rx_ring;
1322 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1324 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1328 ring->head = sport->rx_sgl.length - state.residue;
1329 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1332 if ((count != 0) && (sport->last_residue == state.residue))
1333 lpuart_copy_rx_to_tty(sport);
1335 mod_timer(&sport->lpuart_timer,
1336 jiffies + sport->dma_rx_timeout);
1338 if (uart_port_trylock_irqsave(&sport->port, &flags)) {
1339 sport->last_residue = state.residue;
1340 uart_port_unlock_irqrestore(&sport->port, flags);
1344 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1347 struct circ_buf *ring = &sport->rx_ring;
1349 struct tty_port *port = &sport->port.state->port;
1352 struct dma_chan *chan = sport->dma_rx_chan;
1360 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1361 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1362 sport->rx_dma_rng_buf_len = max_t(int,
1363 sport->rxfifo_size * 2,
1364 sport->rx_dma_rng_buf_len);
1369 if (sport->rx_dma_rng_buf_len < 16)
1370 sport->rx_dma_rng_buf_len = 16;
1372 sport->last_residue = 0;
1373 sport->dma_rx_timeout = max(nsecs_to_jiffies(
1374 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
1376 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1380 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1381 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1385 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1389 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1396 dev_err(sport->port.dev,
1401 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1402 sg_dma_address(&sport->rx_sgl),
1403 sport->rx_sgl.length,
1404 sport->rx_sgl.length / 2,
1407 if (!sport->dma_rx_desc) {
1408 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1412 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1413 sport->dma_rx_desc->callback_param = sport;
1414 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1417 if (lpuart_is_32(sport)) {
1418 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1420 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1422 if (sport->dma_idle_int) {
1423 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);
1425 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);
1428 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1429 sport->port.membase + UARTCR5);
1437 struct lpuart_port *sport = container_of(port,
1439 struct dma_chan *chan = sport->dma_rx_chan;
1442 if (!sport->dma_idle_int)
1443 del_timer_sync(&sport->lpuart_timer);
1445 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1446 kfree(sport->rx_ring.buf);
1447 sport->rx_ring.tail = 0;
1448 sport->rx_ring.head = 0;
1449 sport->dma_rx_desc = NULL;
1450 sport->dma_rx_cookie = -EINVAL;
1456 struct lpuart_port *sport = container_of(port,
1459 u8 modem = readb(sport->port.membase + UARTMODEM) &
1461 writeb(modem, sport->port.membase + UARTMODEM);
1479 writeb(modem, sport->port.membase + UARTMODEM);
1486 struct lpuart_port *sport = container_of(port,
1489 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1491 lpuart32_write(&sport->port, modem, UARTMODIR);
1509 lpuart32_write(&sport->port, modem, UARTMODIR);
1611 static void lpuart_setup_watermark(struct lpuart_port *sport)
1616 cr2 = readb(sport->port.membase + UARTCR2);
1620 writeb(cr2, sport->port.membase + UARTCR2);
1622 val = readb(sport->port.membase + UARTPFIFO);
1624 sport->port.membase + UARTPFIFO);
1628 sport->port.membase + UARTCFIFO);
1631 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1632 readb(sport->port.membase + UARTDR);
1633 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1636 if (uart_console(&sport->port))
1637 sport->rx_watermark = 1;
1638 writeb(0, sport->port.membase + UARTTWFIFO);
1639 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1642 writeb(cr2_saved, sport->port.membase + UARTCR2);
1645 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1649 lpuart_setup_watermark(sport);
1651 cr2 = readb(sport->port.membase + UARTCR2);
1653 writeb(cr2, sport->port.membase + UARTCR2);
1656 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1661 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1665 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1668 val = lpuart32_read(&sport->port, UARTFIFO);
1672 lpuart32_write(&sport->port, val, UARTFIFO);
1675 if (uart_console(&sport->port))
1676 sport->rx_watermark = 1;
1677 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1679 lpuart32_write(&sport->port, val, UARTWATER);
1682 if (!uart_console(&sport->port)) {
1683 val = lpuart32_read(&sport->port, UARTMODIR);
1684 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1685 lpuart32_write(&sport->port, val, UARTMODIR);
1689 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1692 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1696 lpuart32_setup_watermark(sport);
1698 temp = lpuart32_read(&sport->port, UARTCTRL);
1701 lpuart32_write(&sport->port, temp, UARTCTRL);
1704 static void rx_dma_timer_init(struct lpuart_port *sport)
1706 if (sport->dma_idle_int)
1709 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1710 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1711 add_timer(&sport->lpuart_timer);
1714 static void lpuart_request_dma(struct lpuart_port *sport)
1716 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1717 if (IS_ERR(sport->dma_tx_chan)) {
1718 dev_dbg_once(sport->port.dev,
1720 PTR_ERR(sport->dma_tx_chan));
1721 sport->dma_tx_chan = NULL;
1724 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1725 if (IS_ERR(sport->dma_rx_chan)) {
1726 dev_dbg_once(sport->port.dev,
1728 PTR_ERR(sport->dma_rx_chan));
1729 sport->dma_rx_chan = NULL;
1733 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1738 if (uart_console(&sport->port))
1741 if (!sport->dma_tx_chan)
1744 ret = lpuart_dma_tx_request(&sport->port);
1748 init_waitqueue_head(&sport->dma_wait);
1749 sport->lpuart_dma_tx_use = true;
1750 if (lpuart_is_32(sport)) {
1751 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1752 lpuart32_write(&sport->port,
1755 writeb(readb(sport->port.membase + UARTCR5) |
1756 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1762 sport->lpuart_dma_tx_use = false;
1765 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1770 if (uart_console(&sport->port))
1773 if (!sport->dma_rx_chan)
1777 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1779 ret = lpuart_start_rx_dma(sport);
1783 if (!sport->dma_rx_timeout)
1784 sport->dma_rx_timeout = 1;
1786 sport->lpuart_dma_rx_use = true;
1787 rx_dma_timer_init(sport);
1789 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1790 cr3 = readb(sport->port.membase + UARTCR3);
1792 writeb(cr3, sport->port.membase + UARTCR3);
1798 sport->lpuart_dma_rx_use = false;
1801 static void lpuart_hw_setup(struct lpuart_port *sport)
1805 uart_port_lock_irqsave(&sport->port, &flags);
1807 lpuart_setup_watermark_enable(sport);
1809 lpuart_rx_dma_startup(sport);
1810 lpuart_tx_dma_startup(sport);
1812 uart_port_unlock_irqrestore(&sport->port, flags);
1817 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1821 temp = readb(sport->port.membase + UARTPFIFO);
1823 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1825 sport->port.fifosize = sport->txfifo_size;
1827 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1830 lpuart_request_dma(sport);
1831 lpuart_hw_setup(sport);
1836 static void lpuart32_hw_disable(struct lpuart_port *sport)
1840 temp = lpuart32_read(&sport->port, UARTCTRL);
1843 lpuart32_write(&sport->port, temp, UARTCTRL);
1846 static void lpuart32_configure(struct lpuart_port *sport)
1850 temp = lpuart32_read(&sport->port, UARTCTRL);
1851 if (!sport->lpuart_dma_rx_use)
1853 if (!sport->lpuart_dma_tx_use)
1855 lpuart32_write(&sport->port, temp, UARTCTRL);
1858 static void lpuart32_hw_setup(struct lpuart_port *sport)
1862 uart_port_lock_irqsave(&sport->port, &flags);
1864 lpuart32_hw_disable(sport);
1866 lpuart_rx_dma_startup(sport);
1867 lpuart_tx_dma_startup(sport);
1869 lpuart32_setup_watermark_enable(sport);
1870 lpuart32_configure(sport);
1872 uart_port_unlock_irqrestore(&sport->port, flags);
1877 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1881 temp = lpuart32_read(&sport->port, UARTFIFO);
1883 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1885 sport->port.fifosize = sport->txfifo_size;
1887 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1895 if (is_layerscape_lpuart(sport)) {
1896 sport->rxfifo_size = 16;
1897 sport->txfifo_size = 16;
1898 sport->port.fifosize = sport->txfifo_size;
1901 lpuart_request_dma(sport);
1902 lpuart32_hw_setup(sport);
1907 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1909 if (sport->lpuart_dma_rx_use) {
1910 lpuart_dma_rx_free(&sport->port);
1911 sport->lpuart_dma_rx_use = false;
1914 if (sport->lpuart_dma_tx_use) {
1915 if (wait_event_interruptible_timeout(sport->dma_wait,
1916 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1917 sport->dma_tx_in_progress = false;
1918 dmaengine_terminate_sync(sport->dma_tx_chan);
1920 sport->lpuart_dma_tx_use = false;
1923 if (sport->dma_tx_chan)
1924 dma_release_channel(sport->dma_tx_chan);
1925 if (sport->dma_rx_chan)
1926 dma_release_channel(sport->dma_rx_chan);
1931 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1945 lpuart_dma_shutdown(sport);
1950 struct lpuart_port *sport =
1958 temp = lpuart32_read(&sport->port, UARTSTAT);
1959 lpuart32_write(&sport->port, temp, UARTSTAT);
1974 lpuart_dma_shutdown(sport);
1981 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1988 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1989 old_cr2 = readb(sport->port.membase + UARTCR2);
1990 cr3 = readb(sport->port.membase + UARTCR3);
1991 cr4 = readb(sport->port.membase + UARTCR4);
1992 bdh = readb(sport->port.membase + UARTBDH);
1993 modem = readb(sport->port.membase + UARTMODEM);
2025 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2066 * Since timer function acqures sport->port.lock, need to stop before
2069 if (old && sport->lpuart_dma_rx_use)
2070 lpuart_dma_rx_free(&sport->port);
2072 uart_port_lock_irqsave(&sport->port, &flags);
2074 sport->port.read_status_mask = 0;
2076 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
2078 sport->port.read_status_mask |= UARTSR1_FE;
2081 sport->port.ignore_status_mask = 0;
2083 sport->port.ignore_status_mask |= UARTSR1_PE;
2085 sport->port.ignore_status_mask |= UARTSR1_FE;
2091 sport->port.ignore_status_mask |= UARTSR1_OR;
2098 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2102 sport->port.membase + UARTCR2);
2104 sbr = sport->port.uartclk / (16 * baud);
2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2110 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2111 writeb(bdh, sport->port.membase + UARTBDH);
2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2113 writeb(cr3, sport->port.membase + UARTCR3);
2114 writeb(cr1, sport->port.membase + UARTCR1);
2115 writeb(modem, sport->port.membase + UARTMODEM);
2118 writeb(old_cr2, sport->port.membase + UARTCR2);
2120 if (old && sport->lpuart_dma_rx_use) {
2121 if (!lpuart_start_rx_dma(sport))
2122 rx_dma_timer_init(sport);
2124 sport->lpuart_dma_rx_use = false;
2127 uart_port_unlock_irqrestore(&sport->port, flags);
2206 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2209 __lpuart32_serial_setbrg(&sport->port, baudrate,
2210 sport->lpuart_dma_rx_use,
2211 sport->lpuart_dma_tx_use);
2219 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2225 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2226 bd = lpuart32_read(&sport->port, UARTBAUD);
2227 modem = lpuart32_read(&sport->port, UARTMODIR);
2228 sport->is_cs7 = false;
2260 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2301 * Since timer function acqures sport->port.lock, need to stop before
2304 if (old && sport->lpuart_dma_rx_use)
2305 lpuart_dma_rx_free(&sport->port);
2307 uart_port_lock_irqsave(&sport->port, &flags);
2309 sport->port.read_status_mask = 0;
2311 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2313 sport->port.read_status_mask |= UARTSTAT_FE;
2316 sport->port.ignore_status_mask = 0;
2318 sport->port.ignore_status_mask |= UARTSTAT_PE;
2320 sport->port.ignore_status_mask |= UARTSTAT_FE;
2326 sport->port.ignore_status_mask |= UARTSTAT_OR;
2338 lpuart32_write(&sport->port, 0, UARTMODIR);
2339 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2343 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2346 lpuart32_write(&sport->port, bd, UARTBAUD);
2347 lpuart32_serial_setbrg(sport, baud);
2349 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
2351 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2353 lpuart32_write(&sport->port, modem, UARTMODIR);
2356 sport->is_cs7 = true;
2358 if (old && sport->lpuart_dma_rx_use) {
2359 if (!lpuart_start_rx_dma(sport))
2360 rx_dma_timer_init(sport);
2362 sport->lpuart_dma_rx_use = false;
2365 uart_port_unlock_irqrestore(&sport->port, flags);
2477 struct lpuart_port *sport = lpuart_ports[co->index];
2483 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2485 uart_port_lock_irqsave(&sport->port, &flags);
2488 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2491 writeb(cr2, sport->port.membase + UARTCR2);
2493 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2496 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2498 writeb(old_cr2, sport->port.membase + UARTCR2);
2501 uart_port_unlock_irqrestore(&sport->port, flags);
2507 struct lpuart_port *sport = lpuart_ports[co->index];
2513 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2515 uart_port_lock_irqsave(&sport->port, &flags);
2518 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2521 lpuart32_write(&sport->port, cr, UARTCTRL);
2523 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2526 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2528 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2531 uart_port_unlock_irqrestore(&sport->port, flags);
2539 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2545 cr = readb(sport->port.membase + UARTCR2);
2552 cr = readb(sport->port.membase + UARTCR1);
2567 bdh = readb(sport->port.membase + UARTBDH);
2569 bdl = readb(sport->port.membase + UARTBDL);
2573 brfa = readb(sport->port.membase + UARTCR4);
2576 uartclk = lpuart_get_baud_clk_rate(sport);
2583 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2588 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2594 cr = lpuart32_read(&sport->port, UARTCTRL);
2601 cr = lpuart32_read(&sport->port, UARTCTRL);
2616 bd = lpuart32_read(&sport->port, UARTBAUD);
2622 uartclk = lpuart_get_baud_clk_rate(sport);
2629 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2635 struct lpuart_port *sport;
2649 sport = lpuart_ports[co->index];
2650 if (sport == NULL)
2656 if (lpuart_is_32(sport))
2657 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2659 lpuart_console_get_options(sport, &baud, &parity, &bits);
2661 if (lpuart_is_32(sport))
2662 lpuart32_setup_watermark(sport);
2664 lpuart_setup_watermark(sport);
2666 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2793 static int lpuart_global_reset(struct lpuart_port *sport)
2795 struct uart_port *port = &sport->port;
2801 ret = clk_prepare_enable(sport->ipg_clk);
2803 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2807 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2814 bd = lpuart32_read(&sport->port, UARTBAUD);
2817 dev_warn(sport->port.dev,
2819 clk_disable_unprepare(sport->ipg_clk);
2837 clk_disable_unprepare(sport->ipg_clk);
2845 struct lpuart_port *sport;
2850 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2851 if (!sport)
2854 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2855 if (IS_ERR(sport->port.membase))
2856 return PTR_ERR(sport->port.membase);
2858 sport->port.membase += sdata->reg_off;
2859 sport->port.mapbase = res->start + sdata->reg_off;
2860 sport->port.dev = &pdev->dev;
2861 sport->port.type = PORT_LPUART;
2862 sport->devtype = sdata->devtype;
2863 sport->rx_watermark = sdata->rx_watermark;
2864 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
2865 is_imx8qxp_lpuart(sport);
2869 sport->port.irq = ret;
2870 sport->port.iotype = sdata->iotype;
2871 if (lpuart_is_32(sport))
2872 sport->port.ops = &lpuart32_pops;
2874 sport->port.ops = &lpuart_pops;
2875 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2876 sport->port.flags = UPF_BOOT_AUTOCONF;
2878 if (lpuart_is_32(sport))
2879 sport->port.rs485_config = lpuart32_config_rs485;
2881 sport->port.rs485_config = lpuart_config_rs485;
2882 sport->port.rs485_supported = lpuart_rs485_supported;
2884 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2885 if (IS_ERR(sport->ipg_clk)) {
2886 ret = PTR_ERR(sport->ipg_clk);
2891 sport->baud_clk = NULL;
2892 if (is_imx8qxp_lpuart(sport)) {
2893 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2894 if (IS_ERR(sport->baud_clk)) {
2895 ret = PTR_ERR(sport->baud_clk);
2910 sport->port.line = ret;
2912 ret = lpuart_enable_clks(sport);
2915 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2917 lpuart_ports[sport->port.line] = sport;
2919 platform_set_drvdata(pdev, &sport->port);
2921 if (lpuart_is_32(sport)) {
2934 ret = lpuart_global_reset(sport);
2938 ret = uart_get_rs485_mode(&sport->port);
2942 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2946 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2947 DRIVER_NAME, sport);
2954 uart_remove_one_port(&lpuart_reg, &sport->port);
2961 lpuart_disable_clks(sport);
2967 struct lpuart_port *sport = platform_get_drvdata(pdev);
2969 uart_remove_one_port(&lpuart_reg, &sport->port);
2971 lpuart_disable_clks(sport);
2973 if (sport->dma_tx_chan)
2974 dma_release_channel(sport->dma_tx_chan);
2976 if (sport->dma_rx_chan)
2977 dma_release_channel(sport->dma_rx_chan);
2987 struct lpuart_port *sport = platform_get_drvdata(pdev);
2989 lpuart_disable_clks(sport);
2997 struct lpuart_port *sport = platform_get_drvdata(pdev);
2999 return lpuart_enable_clks(sport);
3002 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
3006 if (lpuart_is_32(sport)) {
3007 val = lpuart32_read(&sport->port, UARTCTRL);
3008 baud = lpuart32_read(&sport->port, UARTBAUD);
3011 lpuart32_write(&sport->port, 0, UARTWATER);
3014 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
3020 lpuart32_write(&sport->port, val, UARTCTRL);
3021 lpuart32_write(&sport->port, baud, UARTBAUD);
3023 val = readb(sport->port.membase + UARTCR2);
3028 writeb(val, sport->port.membase + UARTCR2);
3032 static bool lpuart_uport_is_active(struct lpuart_port *sport)
3034 struct tty_port *port = &sport->port.state->port;
3047 (!console_suspend_enabled && uart_console(&sport->port)))
3055 struct lpuart_port *sport = dev_get_drvdata(dev);
3056 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
3058 if (lpuart_uport_is_active(sport))
3059 serial_lpuart_enable_wakeup(sport, !!irq_wake);
3068 struct lpuart_port *sport = dev_get_drvdata(dev);
3073 if (lpuart_uport_is_active(sport)) {
3074 serial_lpuart_enable_wakeup(sport, false);
3077 if (lpuart_is_32(sport)) {
3078 val = lpuart32_read(&sport->port, UARTSTAT);
3079 lpuart32_write(&sport->port, val, UARTSTAT);
3088 struct lpuart_port *sport = dev_get_drvdata(dev);
3091 uart_suspend_port(&lpuart_reg, &sport->port);
3093 if (lpuart_uport_is_active(sport)) {
3094 uart_port_lock_irqsave(&sport->port, &flags);
3095 if (lpuart_is_32(sport)) {
3097 temp = lpuart32_read(&sport->port, UARTCTRL);
3099 lpuart32_write(&sport->port, temp, UARTCTRL);
3102 temp = readb(sport->port.membase + UARTCR2);
3104 writeb(temp, sport->port.membase + UARTCR2);
3106 uart_port_unlock_irqrestore(&sport->port, flags);
3108 if (sport->lpuart_dma_rx_use) {
3116 lpuart_dma_rx_free(&sport->port);
3119 uart_port_lock_irqsave(&sport->port, &flags);
3120 if (lpuart_is_32(sport)) {
3121 temp = lpuart32_read(&sport->port, UARTBAUD);
3122 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3125 writeb(readb(sport->port.membase + UARTCR5) &
3126 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3128 uart_port_unlock_irqrestore(&sport->port, flags);
3131 if (sport->lpuart_dma_tx_use) {
3132 uart_port_lock_irqsave(&sport->port, &flags);
3133 if (lpuart_is_32(sport)) {
3134 temp = lpuart32_read(&sport->port, UARTBAUD);
3136 lpuart32_write(&sport->port, temp, UARTBAUD);
3138 temp = readb(sport->port.membase + UARTCR5);
3140 writeb(temp, sport->port.membase + UARTCR5);
3142 uart_port_unlock_irqrestore(&sport->port, flags);
3143 sport->dma_tx_in_progress = false;
3144 dmaengine_terminate_sync(sport->dma_tx_chan);
3146 } else if (pm_runtime_active(sport->port.dev)) {
3147 lpuart_disable_clks(sport);
3148 pm_runtime_disable(sport->port.dev);
3149 pm_runtime_set_suspended(sport->port.dev);
3155 static void lpuart_console_fixup(struct lpuart_port *sport)
3157 struct tty_port *port = &sport->port.state->port;
3158 struct uart_port *uport = &sport->port;
3168 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3169 console_suspend_enabled && uart_console(&sport->port)) {
3183 struct lpuart_port *sport = dev_get_drvdata(dev);
3186 if (lpuart_uport_is_active(sport)) {
3187 if (lpuart_is_32(sport))
3188 lpuart32_hw_setup(sport);
3190 lpuart_hw_setup(sport);
3191 } else if (pm_runtime_active(sport->port.dev)) {
3192 ret = lpuart_enable_clks(sport);
3195 pm_runtime_set_active(sport->port.dev);
3196 pm_runtime_enable(sport->port.dev);
3199 lpuart_console_fixup(sport);
3200 uart_resume_port(&lpuart_reg, &sport->port);