tty/serial/fsl_lpuart.c

387 		return readl(port->membase + off);
389 		return ioread32be(port->membase + off);
400 		writel(val, port->membase + off);
403 		iowrite32be(val, port->membase + off);
445 	temp = readb(port->membase + UARTCR2);
447 	writeb(temp, port->membase + UARTCR2);
463 	temp = readb(port->membase + UARTCR2);
464 	writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
617 		val = readb(sport->port.membase + UARTCFIFO);
619 		writeb(val, sport->port.membase + UARTCFIFO);
626 	while (!(readb(port->membase + offset) & bit))
650 	writeb(0, sport->port.membase + UARTCR2);
652 	temp = readb(sport->port.membase + UARTPFIFO);
655 			sport->port.membase + UARTPFIFO);
659 			sport->port.membase + UARTCFIFO);
662 	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
663 		readb(sport->port.membase + UARTDR);
664 		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
667 	writeb(0, sport->port.membase + UARTTWFIFO);
668 	writeb(1, sport->port.membase + UARTRWFIFO);
671 	writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
681 	writeb(c, port->membase + UARTDR);
686 	if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
689 	return readb(port->membase + UARTDR);
747 		readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
748 		writeb(ch, port->membase + UARTDR));
793 	temp = readb(port->membase + UARTCR2);
794 	writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
800 		if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
841 	unsigned char sr1 = readb(port->membase + UARTSR1);
842 	unsigned char sfifo = readb(port->membase + UARTSFIFO);
890 	while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
897 		sr = readb(sport->port.membase + UARTSR1);
898 		rx = readb(sport->port.membase + UARTDR);
943 		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
944 		writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
1043 	sts = readb(sport->port.membase + UARTSR1);
1047 		readb(sport->port.membase + UARTDR);
1050 		writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1127 		unsigned char sr = readb(sport->port.membase + UARTSR1);
1133 			cr2 = readb(sport->port.membase + UARTCR2);
1135 			writeb(cr2, sport->port.membase + UARTCR2);
1138 			readb(sport->port.membase + UARTDR);
1153 			if (readb(sport->port.membase + UARTSFIFO) &
1156 				       sport->port.membase + UARTSFIFO);
1158 				       sport->port.membase + UARTCFIFO);
1162 			writeb(cr2, sport->port.membase + UARTCR2);
1423 		writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1424 		       sport->port.membase + UARTCR5);
1454 	u8 modem = readb(sport->port.membase + UARTMODEM) &
1456 	writeb(modem, sport->port.membase + UARTMODEM);
1474 	writeb(modem, sport->port.membase + UARTMODEM);
1513 	reg = readb(port->membase + UARTCR1);
1536 	reg = readb(port->membase + UARTCR1);
1543 	writeb(reg, port->membase + UARTCR1);
1564 	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1569 	writeb(temp, port->membase + UARTCR2);
1611 	cr2 = readb(sport->port.membase + UARTCR2);
1615 	writeb(cr2, sport->port.membase + UARTCR2);
1617 	val = readb(sport->port.membase + UARTPFIFO);
1619 			sport->port.membase + UARTPFIFO);
1623 			sport->port.membase + UARTCFIFO);
1626 	if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1627 		readb(sport->port.membase + UARTDR);
1628 		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1633 	writeb(0, sport->port.membase + UARTTWFIFO);
1634 	writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1637 	writeb(cr2_saved, sport->port.membase + UARTCR2);
1646 	cr2 = readb(sport->port.membase + UARTCR2);
1648 	writeb(cr2, sport->port.membase + UARTCR2);
1750 		writeb(readb(sport->port.membase + UARTCR5) |
1751 		       UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1785 		cr3 = readb(sport->port.membase + UARTCR3);
1787 		writeb(cr3, sport->port.membase + UARTCR3);
1816 	temp = readb(sport->port.membase + UARTPFIFO);
1933 	temp = readb(port->membase + UARTCR2);
1936 	writeb(temp, port->membase + UARTCR2);
1983 	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1984 	old_cr2 = readb(sport->port.membase + UARTCR2);
1985 	cr3 = readb(sport->port.membase + UARTCR3);
1986 	cr4 = readb(sport->port.membase + UARTCR4);
1987 	bdh = readb(sport->port.membase + UARTBDH);
1988 	modem = readb(sport->port.membase + UARTMODEM);
2097 			sport->port.membase + UARTCR2);
2105 	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2106 	writeb(bdh, sport->port.membase + UARTBDH);
2107 	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2108 	writeb(cr3, sport->port.membase + UARTCR3);
2109 	writeb(cr1, sport->port.membase + UARTCR1);
2110 	writeb(modem, sport->port.membase + UARTMODEM);
2113 	writeb(old_cr2, sport->port.membase + UARTCR2);
2460 	writeb(ch, port->membase + UARTDR);
2483 	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2486 	writeb(cr2, sport->port.membase + UARTCR2);
2493 	writeb(old_cr2, sport->port.membase + UARTCR2);
2540 	cr = readb(sport->port.membase + UARTCR2);
2547 	cr = readb(sport->port.membase + UARTCR1);
2562 	bdh = readb(sport->port.membase + UARTBDH);
2564 	bdl = readb(sport->port.membase + UARTBDL);
2568 	brfa = readb(sport->port.membase + UARTCR4);
2702 	if (!device->port.membase)
2712 	if (!device->port.membase)
2727 	if (!device->port.membase)
2749 	if (!device->port.membase)
2753 	device->port.membase += IMX_REG_OFF;
2819 		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2849 	sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2850 	if (IS_ERR(sport->port.membase))
2851 		return PTR_ERR(sport->port.membase);
2853 	sport->port.membase += sdata->reg_off;
3016 		val = readb(sport->port.membase + UARTCR2);
3021 		writeb(val, sport->port.membase + UARTCR2);
3095 			temp = readb(sport->port.membase + UARTCR2);
3097 			writeb(temp, sport->port.membase + UARTCR2);
3118 				writeb(readb(sport->port.membase + UARTCR5) &
3119 				       ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3131 				temp = readb(sport->port.membase + UARTCR5);
3133 				writeb(temp, sport->port.membase + UARTCR5);