serial/8250/8250_pci1xxxx.c

141 	void __iomem *membase;
154 	writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG);
155 	return readl(port->membase + UART_SYSLOCK_REG);
170 	writel(0x0, port->membase + UART_SYSLOCK_REG);
249 		writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG);
251 		writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG);
254 	       port->membase + UART_BAUD_CLK_DIVISOR_REG);
268 	frac_div = readl(port->membase + FRAC_DIV_CFG_REG);
286 			clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
303 	writel(mode_cfg, port->membase + ADCL_CFG_REG);
311 	status = readl(port->membase + UART_BURST_STATUS_REG);
315 			       port->membase + UART_FIFO_CTL);
345 		*burst_buf = readl(port->membase + UART_RX_BURST_FIFO);
353 		rx_buff[*buff_index] = readb(port->membase +
407 		writel(c, port->membase + UART_TX_BURST_FIFO);
418 		writeb(c, port->membase + UART_TX_BYTE_FIFO);
440 		writeb(port->x_char, port->membase + UART_TX);
511 		wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);
521 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
535 	writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);
536 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
642 	writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);
643 	writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);
644 	writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);
686 	regval = readl(priv->membase + UART_DEV_REV_REG);
718 	priv->membase = pci_ioremap_bar(pdev, 0);
719 	if (!priv->membase)
735 		pci_iounmap(pdev, priv->membase);
744 		writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);
787 	pci_iounmap(dev, priv->membase);