Lines Matching refs:outb

303 	outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
309 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
312 outb(oldlcr, baseio + UART_LCR);
326 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
327 outb(oldlcr, baseio + UART_LCR);
333 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
334 outb(oldlcr, baseio + UART_LCR);
340 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
341 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
342 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
343 outb(oldlcr, info->ioaddr + UART_LCR);
349 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
350 outb(oldlcr, baseio + UART_LCR);
357 outb(oldlcr, baseio + UART_LCR);
396 outb(0, io + UART_LCR);
399 outb(0, io + UART_MCR);
402 outb(oldmcr, io + UART_MCR);
441 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
443 outb(info->IER, info->ioaddr + UART_IER);
458 outb(info->IER, info->ioaddr + UART_IER);
480 outb(mcr, mp->ioaddr + UART_MCR);
517 outb(info->MCR, info->ioaddr + UART_MCR);
520 outb(info->MCR, info->ioaddr + UART_MCR);
526 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
528 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
529 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
530 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
639 outb(info->MCR, info->ioaddr + UART_MCR);
643 outb(info->IER, info->ioaddr + UART_IER);
682 outb(info->FCR, info->ioaddr + UART_FCR);
683 outb(cval, info->ioaddr + UART_LCR);
723 outb(fcr, info->ioaddr + UART_FCR);
778 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
780 outb(info->MCR, info->ioaddr + UART_MCR);
789 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
825 outb(info->IER, info->ioaddr + UART_IER);
847 outb(0x00, info->ioaddr + UART_IER);
891 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1141 outb(info->MCR, info->ioaddr + UART_MCR);
1189 outb(val, port->opmode_ioaddr);
1283 outb(info->IER, info->ioaddr + UART_IER);
1286 outb(0, info->ioaddr + UART_IER);
1288 outb(info->IER, info->ioaddr + UART_IER);
1294 outb(info->MCR, info->ioaddr + UART_MCR);
1309 outb(info->IER, info->ioaddr + UART_IER);
1312 outb(0, info->ioaddr + UART_IER);
1314 outb(info->IER, info->ioaddr + UART_IER);
1321 outb(info->MCR, info->ioaddr + UART_MCR);
1474 outb(lcr, info->ioaddr + UART_LCR);
1517 outb(port->FCR | UART_FCR_CLEAR_RCVR,
1574 outb(port->x_char, port->ioaddr + UART_TX);
1593 outb(c, port->ioaddr + UART_TX);
1618 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1752 outb(0, brd->vector + 4);
1753 outb(0, brd->vector + 0x0c);
1781 outb(inb(info->ioaddr + UART_IER) & 0xf0,