drivers/thunderbolt/tmu.c

67 	int ret;
72 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
74 	if (ret)
75 		return ret;
80 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
82 	if (ret)
83 		return ret;
85 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
87 	if (ret)
88 		return ret;
99 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
101 	if (ret)
102 		return ret;
107 		ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
109 		if (ret)
110 			return ret;
115 		ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
119 	return ret;
124 	int ret;
127 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
129 	if (ret)
137 	int ret;
140 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
142 	if (ret)
143 		return ret;
151 	int ret;
154 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
156 	if (ret)
157 		return ret;
170 	int ret;
172 	ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1);
173 	if (ret)
174 		return ret;
207 	int ret;
210 	ret = tb_port_read(port, &val, TB_CFG_PORT,
212 	if (ret)
220 	int ret;
223 	ret = tb_port_read(port, &val, TB_CFG_PORT,
225 	if (ret)
234 	int ret;
240 	ret = tb_port_read(port, &val, TB_CFG_PORT,
242 	if (ret)
243 		return ret;
258 	int ret;
265 	ret = tb_port_read(port, &val, TB_CFG_PORT,
267 	if (ret)
268 		return ret;
275 	ret = tb_port_write(port, &val, TB_CFG_PORT,
277 	if (ret)
278 		return ret;
280 	ret = tb_port_read(port, &val, TB_CFG_PORT,
282 	if (ret)
283 		return ret;
297 	int ret;
303 	ret = tb_port_read(port, &val, TB_CFG_PORT,
305 	if (ret)
306 		return ret;
335 	int ret;
345 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
346 	if (ret)
347 		return ret;
360 	int ret, rate;
369 	ret = tb_switch_tmu_rate_read(sw);
370 	if (ret < 0)
371 		return ret;
372 	rate = ret;
412 	int ret;
417 	ret = tb_switch_find_cap(sw, TB_SWITCH_CAP_TMU);
418 	if (ret > 0)
419 		sw->tmu.cap = ret;
429 	ret = tmu_mode_init(sw);
430 	if (ret)
431 		return ret;
449 	int i, ret, retries = 100;
462 	ret = tb_sw_read(root_switch, gm_local_time, TB_CFG_SWITCH,
465 	if (ret)
466 		return ret;
480 	ret = tb_switch_tmu_set_time_disruption(sw, true);
481 	if (ret)
482 		return ret;
492 	ret = tb_sw_write(sw, &local_time, TB_CFG_SWITCH,
494 	if (ret)
507 	ret = tb_sw_write(sw, &post_time, TB_CFG_SWITCH, post_time_offset, 2);
508 	if (ret)
511 	ret = tb_sw_write(sw, &post_time_high, TB_CFG_SWITCH,
513 	if (ret)
518 		ret = tb_sw_read(sw, &post_time, TB_CFG_SWITCH,
520 		if (ret)
525 		ret = -ETIMEDOUT;
533 	return ret;
538 	int ret;
547 	ret = tb_port_tmu_rate_write(down, 0);
548 	if (ret)
549 		return ret;
567 		int ret;
582 		ret = tb_switch_tmu_rate_write(sw, tmu_rates[TB_SWITCH_TMU_MODE_OFF]);
583 		if (ret)
584 			return ret;
587 		ret = tb_port_tmu_time_sync_disable(down);
588 		if (ret)
589 			return ret;
596 			ret = tb_port_tmu_unidirectional_disable(down);
597 			if (ret)
598 				return ret;
602 			ret = disable_enhanced(up, down);
603 			if (ret)
604 				return ret;
665 	int ret;
670 	ret = tb_port_tmu_unidirectional_disable(up);
671 	if (ret)
672 		return ret;
674 	ret = tb_port_tmu_unidirectional_disable(down);
675 	if (ret)
678 	ret = tb_switch_tmu_rate_write(sw, tmu_rates[TB_SWITCH_TMU_MODE_HIFI_BI]);
679 	if (ret)
682 	ret = tb_port_tmu_time_sync_enable(up);
683 	if (ret)
686 	ret = tb_port_tmu_time_sync_enable(down);
687 	if (ret)
694 	return ret;
702 	int ret;
704 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
706 	if (ret)
707 		return ret;
711 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
713 	if (ret)
714 		return ret;
729 	int ret;
733 	ret = tb_switch_tmu_rate_write(tb_switch_parent(sw),
735 	if (ret)
736 		return ret;
738 	ret = tb_switch_set_tmu_mode_params(sw, sw->tmu.mode_request);
739 	if (ret)
740 		return ret;
742 	ret = tb_port_tmu_unidirectional_enable(up);
743 	if (ret)
746 	ret = tb_port_tmu_time_sync_enable(up);
747 	if (ret)
750 	ret = tb_port_tmu_unidirectional_enable(down);
751 	if (ret)
754 	ret = tb_port_tmu_time_sync_enable(down);
755 	if (ret)
762 	return ret;
773 	int ret;
776 	ret = tb_switch_set_tmu_mode_params(sw, sw->tmu.mode_request);
777 	if (ret)
778 		return ret;
783 	ret = tb_port_set_tmu_mode_params(up, sw->tmu.mode_request);
784 	if (ret)
787 	ret = tb_port_tmu_rate_write(up, rate);
788 	if (ret)
791 	ret = tb_port_tmu_enhanced_enable(up, true);
792 	if (ret)
795 	ret = tb_port_set_tmu_mode_params(down, sw->tmu.mode_request);
796 	if (ret)
799 	ret = tb_port_tmu_rate_write(down, rate);
800 	if (ret)
803 	ret = tb_port_tmu_enhanced_enable(down, true);
804 	if (ret)
811 	return ret;
864 	int ret;
873 		ret = tb_port_tmu_set_unidirectional(down, true);
874 		if (ret)
876 		ret = tb_switch_tmu_rate_write(tb_switch_parent(sw), rate);
877 		if (ret)
882 		ret = tb_port_tmu_set_unidirectional(down, false);
883 		if (ret)
885 		ret = tb_switch_tmu_rate_write(sw, rate);
886 		if (ret)
895 	ret = tb_switch_set_tmu_mode_params(sw, sw->tmu.mode_request);
896 	if (ret)
903 		ret = tb_port_tmu_set_unidirectional(up, true);
904 		if (ret)
909 		ret = tb_port_tmu_set_unidirectional(up, false);
910 		if (ret)
919 	ret = tb_port_tmu_time_sync_enable(down);
920 	if (ret)
923 	ret = tb_port_tmu_time_sync_enable(up);
924 	if (ret)
931 	return ret;
944 	int ret;
952 		ret = tb_switch_tmu_disable_objections(sw);
953 		if (ret)
954 			return ret;
957 	ret = tb_switch_tmu_set_time_disruption(sw, true);
958 	if (ret)
959 		return ret;
971 				ret = tb_switch_tmu_enable_unidirectional(sw);
975 				ret = tb_switch_tmu_enable_bidirectional(sw);
978 				ret = tb_switch_tmu_enable_enhanced(sw);
981 				ret = -EINVAL;
987 			ret = tb_switch_tmu_change_mode(sw);
989 			ret = -EINVAL;
998 		ret = tb_switch_tmu_rate_write(sw, tmu_rates[sw->tmu.mode_request]);
1001 	if (ret) {
1003 			   tmu_mode_name(sw->tmu.mode_request), ret);