Lines Matching refs:data
139 * struct exynos_tmu_data : A structure to hold the private data of the TMU
151 * @min_efuse_value: minimum valid trimming data
152 * @max_efuse_value: maximum valid trimming data
190 void (*tmu_set_low_temp)(struct exynos_tmu_data *data, u8 temp);
191 void (*tmu_set_high_temp)(struct exynos_tmu_data *data, u8 temp);
192 void (*tmu_set_crit_temp)(struct exynos_tmu_data *data, u8 temp);
193 void (*tmu_disable_low)(struct exynos_tmu_data *data);
194 void (*tmu_disable_high)(struct exynos_tmu_data *data);
197 int (*tmu_read)(struct exynos_tmu_data *data);
198 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
199 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
206 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
208 if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
209 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM;
212 (data->temp_error2 - data->temp_error1) /
214 data->temp_error1;
221 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
223 if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
224 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM;
226 return (temp_code - data->temp_error1) *
228 (data->temp_error2 - data->temp_error1) +
232 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
235 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
238 data->temp_error1 = trim_info & tmu_temp_mask;
239 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
242 if (!data->temp_error1 ||
243 (data->min_efuse_value > data->temp_error1) ||
244 (data->temp_error1 > data->max_efuse_value))
245 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
247 if (!data->temp_error2)
248 data->temp_error2 =
249 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
255 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
259 mutex_lock(&data->lock);
260 clk_enable(data->clk);
261 if (!IS_ERR(data->clk_sec))
262 clk_enable(data->clk_sec);
264 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
268 data->tmu_initialize(pdev);
269 data->tmu_clear_irqs(data);
272 if (!IS_ERR(data->clk_sec))
273 clk_disable(data->clk_sec);
274 clk_disable(data->clk);
275 mutex_unlock(&data->lock);
282 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
283 struct thermal_zone_device *tzd = data->tzd;
289 if (data->soc == SOC_ARCH_EXYNOS5433)
297 mutex_lock(&data->lock);
298 clk_enable(data->clk);
300 data->tmu_set_crit_temp(data, temp / MCELSIUS);
302 clk_disable(data->clk);
303 mutex_unlock(&data->lock);
308 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
310 if (data->soc == SOC_ARCH_EXYNOS4412 ||
311 data->soc == SOC_ARCH_EXYNOS3250)
315 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
318 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
328 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
330 mutex_lock(&data->lock);
331 clk_enable(data->clk);
332 data->tmu_control(pdev, on);
333 data->enabled = on;
334 clk_disable(data->clk);
335 mutex_unlock(&data->lock);
338 static void exynos_tmu_update_bit(struct exynos_tmu_data *data, int reg_off,
343 interrupt_en = readl(data->base + reg_off);
348 writel(interrupt_en, data->base + reg_off);
351 static void exynos_tmu_update_temp(struct exynos_tmu_data *data, int reg_off,
358 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
361 th = readl(data->base + reg_off);
363 th |= temp_to_code(data, temp) << bit_off;
364 writel(th, data->base + reg_off);
367 static void exynos4210_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp)
375 static void exynos4210_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp)
377 temp = temp_to_code(data, temp);
378 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + 4);
379 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
383 static void exynos4210_tmu_disable_low(struct exynos_tmu_data *data)
388 static void exynos4210_tmu_disable_high(struct exynos_tmu_data *data)
390 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
394 static void exynos4210_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp)
402 temp = temp_to_code(data, temp);
403 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + 12);
404 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
410 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
412 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
414 writeb(0, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
417 static void exynos4412_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp)
419 exynos_tmu_update_temp(data, EXYNOS_THD_TEMP_FALL, 0, temp);
420 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
424 static void exynos4412_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp)
426 exynos_tmu_update_temp(data, EXYNOS_THD_TEMP_RISE, 8, temp);
427 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
431 static void exynos4412_tmu_disable_low(struct exynos_tmu_data *data)
433 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_INTEN,
437 static void exynos4412_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp)
439 exynos_tmu_update_temp(data, EXYNOS_THD_TEMP_RISE, 24, temp);
440 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_CONTROL,
446 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
449 if (data->soc == SOC_ARCH_EXYNOS3250 ||
450 data->soc == SOC_ARCH_EXYNOS4412 ||
451 data->soc == SOC_ARCH_EXYNOS5250) {
452 if (data->soc == SOC_ARCH_EXYNOS3250) {
453 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
455 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
457 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
459 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
463 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
464 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
466 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
468 sanitize_temp_error(data, trim_info);
471 static void exynos5433_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp)
473 exynos_tmu_update_temp(data, EXYNOS5433_THD_TEMP_FALL3_0, 0, temp);
474 exynos_tmu_update_bit(data, EXYNOS5433_TMU_REG_INTEN,
478 static void exynos5433_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp)
480 exynos_tmu_update_temp(data, EXYNOS5433_THD_TEMP_RISE3_0, 8, temp);
481 exynos_tmu_update_bit(data, EXYNOS5433_TMU_REG_INTEN,
485 static void exynos5433_tmu_disable_low(struct exynos_tmu_data *data)
487 exynos_tmu_update_bit(data, EXYNOS5433_TMU_REG_INTEN,
491 static void exynos5433_tmu_disable_high(struct exynos_tmu_data *data)
493 exynos_tmu_update_bit(data, EXYNOS5433_TMU_REG_INTEN,
497 static void exynos5433_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp)
499 exynos_tmu_update_temp(data, EXYNOS5433_THD_TEMP_RISE7_4, 24, temp);
500 exynos_tmu_update_bit(data, EXYNOS_TMU_REG_CONTROL,
502 exynos_tmu_update_bit(data, EXYNOS5433_TMU_REG_INTEN,
508 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
512 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
513 sanitize_temp_error(data, trim_info);
521 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
527 data->cal_type = TYPE_TWO_POINT_TRIMMING;
531 data->cal_type = TYPE_ONE_POINT_TRIMMING;
539 static void exynos7_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp)
541 exynos_tmu_update_temp(data, EXYNOS7_THD_TEMP_FALL7_6 + 12, 0, temp);
542 exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN,
546 static void exynos7_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp)
548 exynos_tmu_update_temp(data, EXYNOS7_THD_TEMP_RISE7_6 + 12, 16, temp);
549 exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN,
553 static void exynos7_tmu_disable_low(struct exynos_tmu_data *data)
555 exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN,
559 static void exynos7_tmu_disable_high(struct exynos_tmu_data *data)
561 exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN,
565 static void exynos7_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp)
571 exynos_tmu_update_temp(data, EXYNOS7_THD_TEMP_RISE7_6 + 0, 16, temp);
572 exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN,
578 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
581 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
582 sanitize_temp_error(data, trim_info);
587 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
590 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
597 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
602 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
605 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
614 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
615 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
620 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
623 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
633 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
638 struct exynos_tmu_data *data = thermal_zone_device_priv(tz);
641 if (!data || !data->tmu_read)
643 else if (!data->enabled)
650 mutex_lock(&data->lock);
651 clk_enable(data->clk);
653 value = data->tmu_read(data);
657 *temp = code_to_temp(data, value) * MCELSIUS;
659 clk_disable(data->clk);
660 mutex_unlock(&data->lock);
666 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
674 if (data->soc == SOC_ARCH_EXYNOS7) {
677 val |= (temp_to_code(data, temp) <<
683 val |= (temp_to_code(data, temp) <<
694 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
700 if (data->soc == SOC_ARCH_EXYNOS5260)
702 else if (data->soc == SOC_ARCH_EXYNOS5433)
704 else if (data->soc == SOC_ARCH_EXYNOS7)
709 val = readl(data->base + emul_con);
710 val = get_emul_con_reg(data, val, temp);
711 writel(val, data->base + emul_con);
716 struct exynos_tmu_data *data = thermal_zone_device_priv(tz);
719 if (data->soc == SOC_ARCH_EXYNOS4210)
725 mutex_lock(&data->lock);
726 clk_enable(data->clk);
727 data->tmu_set_emulation(data, temp);
728 clk_disable(data->clk);
729 mutex_unlock(&data->lock);
740 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
742 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
748 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
750 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
753 static int exynos7_tmu_read(struct exynos_tmu_data *data)
755 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
761 struct exynos_tmu_data *data = id;
763 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
765 mutex_lock(&data->lock);
766 clk_enable(data->clk);
769 data->tmu_clear_irqs(data);
771 clk_disable(data->clk);
772 mutex_unlock(&data->lock);
777 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
782 if (data->soc == SOC_ARCH_EXYNOS5260) {
785 } else if (data->soc == SOC_ARCH_EXYNOS7) {
788 } else if (data->soc == SOC_ARCH_EXYNOS5433) {
796 val_irq = readl(data->base + tmu_intstat);
805 writel(val_irq, data->base + tmu_intclear);
811 .data = (const void *)SOC_ARCH_EXYNOS3250,
814 .data = (const void *)SOC_ARCH_EXYNOS4210,
817 .data = (const void *)SOC_ARCH_EXYNOS4412,
820 .data = (const void *)SOC_ARCH_EXYNOS5250,
823 .data = (const void *)SOC_ARCH_EXYNOS5260,
826 .data = (const void *)SOC_ARCH_EXYNOS5420,
829 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO,
832 .data = (const void *)SOC_ARCH_EXYNOS5433,
835 .data = (const void *)SOC_ARCH_EXYNOS7,
843 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
846 if (!data || !pdev->dev.of_node)
849 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
850 if (data->irq <= 0) {
860 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
861 if (!data->base) {
866 data->soc = (uintptr_t)of_device_get_match_data(&pdev->dev);
868 switch (data->soc) {
870 data->tmu_set_low_temp = exynos4210_tmu_set_low_temp;
871 data->tmu_set_high_temp = exynos4210_tmu_set_high_temp;
872 data->tmu_disable_low = exynos4210_tmu_disable_low;
873 data->tmu_disable_high = exynos4210_tmu_disable_high;
874 data->tmu_set_crit_temp = exynos4210_tmu_set_crit_temp;
875 data->tmu_initialize = exynos4210_tmu_initialize;
876 data->tmu_control = exynos4210_tmu_control;
877 data->tmu_read = exynos4210_tmu_read;
878 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
879 data->gain = 15;
880 data->reference_voltage = 7;
881 data->efuse_value = 55;
882 data->min_efuse_value = 40;
883 data->max_efuse_value = 100;
891 data->tmu_set_low_temp = exynos4412_tmu_set_low_temp;
892 data->tmu_set_high_temp = exynos4412_tmu_set_high_temp;
893 data->tmu_disable_low = exynos4412_tmu_disable_low;
894 data->tmu_disable_high = exynos4210_tmu_disable_high;
895 data->tmu_set_crit_temp = exynos4412_tmu_set_crit_temp;
896 data->tmu_initialize = exynos4412_tmu_initialize;
897 data->tmu_control = exynos4210_tmu_control;
898 data->tmu_read = exynos4412_tmu_read;
899 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
900 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
901 data->gain = 8;
902 data->reference_voltage = 16;
903 data->efuse_value = 55;
904 if (data->soc != SOC_ARCH_EXYNOS5420 &&
905 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
906 data->min_efuse_value = 40;
908 data->min_efuse_value = 0;
909 data->max_efuse_value = 100;
912 data->tmu_set_low_temp = exynos5433_tmu_set_low_temp;
913 data->tmu_set_high_temp = exynos5433_tmu_set_high_temp;
914 data->tmu_disable_low = exynos5433_tmu_disable_low;
915 data->tmu_disable_high = exynos5433_tmu_disable_high;
916 data->tmu_set_crit_temp = exynos5433_tmu_set_crit_temp;
917 data->tmu_initialize = exynos5433_tmu_initialize;
918 data->tmu_control = exynos5433_tmu_control;
919 data->tmu_read = exynos4412_tmu_read;
920 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
921 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
922 data->gain = 8;
924 data->reference_voltage = 23;
926 data->reference_voltage = 16;
927 data->efuse_value = 75;
928 data->min_efuse_value = 40;
929 data->max_efuse_value = 150;
932 data->tmu_set_low_temp = exynos7_tmu_set_low_temp;
933 data->tmu_set_high_temp = exynos7_tmu_set_high_temp;
934 data->tmu_disable_low = exynos7_tmu_disable_low;
935 data->tmu_disable_high = exynos7_tmu_disable_high;
936 data->tmu_set_crit_temp = exynos7_tmu_set_crit_temp;
937 data->tmu_initialize = exynos7_tmu_initialize;
938 data->tmu_control = exynos7_tmu_control;
939 data->tmu_read = exynos7_tmu_read;
940 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
941 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
942 data->gain = 9;
943 data->reference_voltage = 17;
944 data->efuse_value = 75;
945 data->min_efuse_value = 15;
946 data->max_efuse_value = 100;
953 data->cal_type = TYPE_ONE_POINT_TRIMMING;
959 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
967 data->base_second = devm_ioremap(&pdev->dev, res.start,
969 if (!data->base_second) {
979 struct exynos_tmu_data *data = thermal_zone_device_priv(tz);
981 mutex_lock(&data->lock);
982 clk_enable(data->clk);
985 data->tmu_set_low_temp(data, low / MCELSIUS);
987 data->tmu_disable_low(data);
989 data->tmu_set_high_temp(data, high / MCELSIUS);
991 data->tmu_disable_high(data);
993 clk_disable(data->clk);
994 mutex_unlock(&data->lock);
1007 struct exynos_tmu_data *data;
1010 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1012 if (!data)
1015 platform_set_drvdata(pdev, data);
1016 mutex_init(&data->lock);
1040 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1041 if (IS_ERR(data->clk)) {
1043 return PTR_ERR(data->clk);
1046 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1047 if (IS_ERR(data->clk_sec)) {
1048 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1050 return PTR_ERR(data->clk_sec);
1053 ret = clk_prepare(data->clk_sec);
1060 ret = clk_prepare(data->clk);
1066 switch (data->soc) {
1069 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1070 if (IS_ERR(data->sclk)) {
1072 ret = PTR_ERR(data->sclk);
1075 ret = clk_prepare_enable(data->sclk);
1092 data->tzd = devm_thermal_of_zone_register(&pdev->dev, 0, data,
1094 if (IS_ERR(data->tzd)) {
1095 ret = PTR_ERR(data->tzd);
1108 ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL,
1112 dev_name(&pdev->dev), data);
1114 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1122 clk_disable_unprepare(data->sclk);
1124 clk_unprepare(data->clk);
1126 if (!IS_ERR(data->clk_sec))
1127 clk_unprepare(data->clk_sec);
1133 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1137 clk_disable_unprepare(data->sclk);
1138 clk_unprepare(data->clk);
1139 if (!IS_ERR(data->clk_sec))
1140 clk_unprepare(data->clk_sec);