thermal/mediatek/auxadc_thermal.c

307 	struct mtk_thermal *mt;
350 	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
705  * @mt:	The thermal controller
712 static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
719 	tmp /= mt->conf->cali_val + mt->o_slope;
720 	tmp /= 10000 + mt->adc_ge;
721 	tmp *= raw - mt->vts[sensno] - 3350;
724 	return mt->degc_cali * 500 - tmp;
727 static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
740 	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
741 	g_oe = mt->adc_oe - 512;
742 	format_1 = mt->vts[VTS2] + 3105 - g_oe;
743 	format_2 = (mt->degc_cali * 10) >> 1;
749 	if (mt->o_slope_sign == 0)
750 		tmp = tmp / (165 - mt->o_slope);
752 		tmp = tmp / (165 + mt->o_slope);
757 static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
766 	tmp /= 4096 - 512 + mt->adc_ge;
768 	tmp *= raw - mt->vts[sensno] - 2900;
770 	return mt->degc_cali * 500 - tmp;
782 	struct mtk_thermal *mt = bank->mt;
785 	if (mt->conf->need_switch_bank) {
786 		mutex_lock(&mt->lock);
788 		val = readl(mt->thermal_base + PTPCORESEL);
791 		writel(val, mt->thermal_base + PTPCORESEL);
803 	struct mtk_thermal *mt = bank->mt;
805 	if (mt->conf->need_switch_bank)
806 		mutex_unlock(&mt->lock);
818 	struct mtk_thermal *mt = bank->mt;
819 	const struct mtk_thermal_data *conf = mt->conf;
824 		raw = readl(mt->thermal_base + conf->msr[i]);
826 		temp = mt->raw_to_mcelsius(
827 			mt, conf->bank_data[bank->id].sensors[i], raw);
850 	struct mtk_thermal *mt = thermal_zone_device_priv(tz);
854 	for (i = 0; i < mt->conf->num_banks; i++) {
855 		struct mtk_thermal_bank *bank = &mt->banks[i];
873 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
877 	struct mtk_thermal_bank *bank = &mt->banks[num];
878 	const struct mtk_thermal_data *conf = mt->conf;
881 	int offset = mt->conf->controller_offset[ctrl_id];
882 	void __iomem *controller_base = mt->thermal_base + offset;
885 	bank->mt = mt;
933 	if (mt->conf->version == MTK_THERMAL_V1) {
970 		       mt->thermal_base + conf->adcpnp[i]);
992 static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
999 	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
1001 	for (i = 0; i < mt->conf->num_sensors; i++) {
1002 		switch (mt->conf->vts_index[i]) {
1004 			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
1007 			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
1010 			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
1013 			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
1016 			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
1019 			mt->vts[VTSABB] =
1027 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
1030 		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
1032 		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
1037 static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
1042 	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
1043 	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
1044 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
1045 	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
1046 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
1047 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
1048 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
1049 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
1054 static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
1059 	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
1060 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
1061 	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
1062 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
1063 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
1064 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
1065 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
1068 		mt->o_slope = 0;
1074 					    struct mtk_thermal *mt)
1082 	mt->adc_ge = 512;
1083 	mt->adc_oe = 512;
1084 	for (i = 0; i < mt->conf->num_sensors; i++)
1085 		mt->vts[i] = 260;
1086 	mt->degc_cali = 40;
1087 	mt->o_slope = 0;
1109 	switch (mt->conf->version) {
1111 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
1114 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
1117 		ret = mtk_thermal_extract_efuse_v3(mt, buf);
1168 static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
1173 	if (!mt->conf->apmixed_buffer_ctl_reg)
1176 	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1177 	tmp &= mt->conf->apmixed_buffer_ctl_mask;
1178 	tmp |= mt->conf->apmixed_buffer_ctl_set;
1179 	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1183 static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1189 	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1190 	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1191 	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1198 	struct mtk_thermal *mt;
1203 	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1204 	if (!mt)
1207 	mt->conf = of_device_get_match_data(&pdev->dev);
1209 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1210 	if (IS_ERR(mt->thermal_base))
1211 		return PTR_ERR(mt->thermal_base);
1213 	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1217 	mutex_init(&mt->lock);
1219 	mt->dev = &pdev->dev;
1257 	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
1258 	if (IS_ERR(mt->clk_auxadc)) {
1259 		ret = PTR_ERR(mt->clk_auxadc);
1264 	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
1265 	if (IS_ERR(mt->clk_peri_therm)) {
1266 		ret = PTR_ERR(mt->clk_peri_therm);
1271 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
1273 	if (mt->conf->version != MTK_THERMAL_V1)
1274 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
1276 	if (mt->conf->version == MTK_THERMAL_V1)
1277 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1278 	else if (mt->conf->version == MTK_THERMAL_V2)
1279 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1281 		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1283 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1284 		for (i = 0; i < mt->conf->num_banks; i++)
1285 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1288 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,