staging/vme_user/vme_tsi148.c

126 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);
146 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),
147 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),
148 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));
151 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),
152 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));
172 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
173 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
174 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
250 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
251 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
383 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
405 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
409 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
418 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
422 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
443 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
532 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
625 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
628 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
630 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
632 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
634 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
636 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
638 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
890 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1049 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1052 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1054 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1056 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1058 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1060 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1062 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1366 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1368 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1382 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1387 	result = ioread32be(image->kern_base + offset);
1390 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1767 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1827 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1851 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1975 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1976 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1977 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2029 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2048 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2052 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2080 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2084 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2098 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2119 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2187 	cbar = ioread32be(bridge->base + TSI148_CBAR);
2199 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2232 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2448 	data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2476 	data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2577 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)