staging/vme_user/vme_fake.c

49 	u32 cycle;
57 	u32 cycle;
156 			  dma_addr_t buf_base, u32 aspace, u32 cycle)
213 	bridge->slaves[i].cycle = cycle;
225 			  dma_addr_t *buf_base, u32 *aspace, u32 *cycle)
241 	*cycle = bridge->slaves[i].cycle;
253 			   u32 aspace, u32 cycle, u32 dwidth)
321 	bridge->masters[i].cycle = cycle;
339 			     u32 *aspace, u32 *cycle, u32 *dwidth)
352 	*cycle = bridge->masters[i].cycle;
360 			   u32 *aspace, u32 *cycle, u32 *dwidth)
367 				   cycle, dwidth);
375 			  u32 aspace, u32 cycle)
399 		/* First make sure that the cycle and address space match */
400 		if ((lm_aspace == aspace) && (lm_cycle == cycle)) {
415 					   u32 aspace, u32 cycle)
429 		if (cycle != bridge->slaves[i].cycle)
441 	fake_lm_check(bridge, addr, aspace, cycle);
448 					     u32 aspace, u32 cycle)
459 		if (cycle != bridge->slaves[i].cycle)
474 	fake_lm_check(bridge, addr, aspace, cycle);
481 					     u32 aspace, u32 cycle)
492 		if (cycle != bridge->slaves[i].cycle)
507 	fake_lm_check(bridge, addr, aspace, cycle);
516 	u32 aspace, cycle, dwidth;
532 	cycle = priv->masters[i].cycle;
541 	 * cycle configured for the transfer is used and splits it
543 	 * overhead of needlessly forcing small transfers for the entire cycle.
546 		*(u8 *)buf = fake_vmeread8(priv, addr, aspace, cycle);
555 						addr + done, aspace, cycle);
560 						addr + done, aspace, cycle);
570 					aspace, cycle);
577 					aspace, cycle);
584 					aspace, cycle);
592 					aspace, cycle);
598 				cycle);
612 					      u32 aspace, u32 cycle)
622 		if (cycle != bridge->slaves[i].cycle)
637 	fake_lm_check(bridge, addr, aspace, cycle);
642 					       u32 aspace, u32 cycle)
652 		if (cycle != bridge->slaves[i].cycle)
667 	fake_lm_check(bridge, addr, aspace, cycle);
672 					       u32 aspace, u32 cycle)
682 		if (cycle != bridge->slaves[i].cycle)
697 	fake_lm_check(bridge, addr, aspace, cycle);
704 	u32 aspace, cycle, dwidth;
721 	cycle = bridge->masters[i].cycle;
730 		fake_vmewrite8(bridge, (u8 *)buf, addr, aspace, cycle);
740 					       addr + done, aspace, cycle);
745 						addr + done, aspace, cycle);
755 					addr + done, aspace, cycle);
762 					addr + done, aspace, cycle);
769 				       aspace, cycle);
777 					addr + done, aspace, cycle);
784 			       cycle);
797  * Perform an RMW cycle on the VME bus.
806 	u32 aspace, cycle;
817 	cycle = bridge->masters[i].cycle;
823 	tmp = fake_vmeread32(bridge, base + offset, aspace, cycle);
831 		fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle);
848 		       u32 aspace, u32 cycle)
883 	bridge->lm_cycle = cycle;
895 		       u32 *aspace, u32 *cycle)
905 	*cycle = bridge->lm_cycle;