most/dim2/hal.c

78 	struct dim2_regs __iomem *dim2; /* DIM2 core base address */
147 	writel(val, &g.dim2->MADR);
150 	while ((readl(&g.dim2->MCTL) & 1) != 1)
153 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
163 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
164 	writel(0, &g.dim2->MDAT0);
174 	return readl((&g.dim2->MDAT0) + mdat_idx);
181 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
184 		writel(value[0], &g.dim2->MDAT0);
186 		writel(value[1], &g.dim2->MDAT1);
188 		writel(value[2], &g.dim2->MDAT2);
190 		writel(value[3], &g.dim2->MDAT3);
192 	writel(mask[0], &g.dim2->MDWE0);
193 	writel(mask[1], &g.dim2->MDWE1);
194 	writel(mask[2], &g.dim2->MDWE2);
195 	writel(mask[3], &g.dim2->MDWE3);
359 	writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
365 	writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
374 	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
518 	writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
523 	writel(0, &g.dim2->MIEN);
526 	writel(0xFFFFFFFF, &g.dim2->ACSR0);
527 	writel(0xFFFFFFFF, &g.dim2->ACSR1);
530 	writel(0, &g.dim2->ACMR0);
531 	writel(0, &g.dim2->ACMR1);
543 	       &g.dim2->MLBC0);
546 	writel(0xFFFFFFFF, &g.dim2->HCMR0);
547 	writel(0xFFFFFFFF, &g.dim2->HCMR1);
550 	writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
554 	       true << ACTL_SCE_BIT, &g.dim2->ACTL);
562 	u32 const c1 = readl(&g.dim2->MLBC1);
565 	writel(c1 & nda_mask, &g.dim2->MLBC1);
566 	return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
567 	       (readl(&g.dim2->MLBC0) & mask0) != 0;
590 	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
728 	g.dim2 = dim_base_address;
776 	writel(0, &g.dim2->MS0);
777 	writel(0, &g.dim2->MS1);
824 		writel(bit_mask(20), &g.dim2->MIEN);
891 		writel(0, &g.dim2->MIEN);