sunxi/cedrus/cedrus_hw.c

69 	cedrus_write(ctx->dev, VE_MODE, reg);
74 void cedrus_engine_disable(struct cedrus_dev *dev)
76 	cedrus_write(dev, VE_MODE, VE_MODE_DISABLED);
79 void cedrus_dst_format_set(struct cedrus_dev *dev,
92 		cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
95 		cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg);
99 		cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg);
105 		cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
108 		cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
116 	struct cedrus_dev *dev = data;
125 	if (!cancel_delayed_work(&dev->watchdog_work))
128 	ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
130 		v4l2_err(&dev->v4l2_dev,
147 	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
155 	struct cedrus_dev *dev;
158 	dev = container_of(to_delayed_work(work),
161 	ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
165 	v4l2_err(&dev->v4l2_dev, "frame processing timed out!\n");
166 	reset_control_reset(dev->rstc);
167 	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
173 	struct cedrus_dev *dev = dev_get_drvdata(device);
175 	clk_disable_unprepare(dev->ram_clk);
176 	clk_disable_unprepare(dev->mod_clk);
177 	clk_disable_unprepare(dev->ahb_clk);
179 	reset_control_assert(dev->rstc);
186 	struct cedrus_dev *dev = dev_get_drvdata(device);
189 	ret = reset_control_reset(dev->rstc);
191 		dev_err(dev->dev, "Failed to apply reset\n");
196 	ret = clk_prepare_enable(dev->ahb_clk);
198 		dev_err(dev->dev, "Failed to enable AHB clock\n");
203 	ret = clk_prepare_enable(dev->mod_clk);
205 		dev_err(dev->dev, "Failed to enable MOD clock\n");
210 	ret = clk_prepare_enable(dev->ram_clk);
212 		dev_err(dev->dev, "Failed to enable RAM clock\n");
220 	clk_disable_unprepare(dev->mod_clk);
222 	clk_disable_unprepare(dev->ahb_clk);
224 	reset_control_assert(dev->rstc);
229 int cedrus_hw_probe(struct cedrus_dev *dev)
235 	variant = of_device_get_match_data(dev->dev);
239 	dev->capabilities = variant->capabilities;
241 	irq_dec = platform_get_irq(dev->pdev, 0);
244 	ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq,
245 			       0, dev_name(dev->dev), dev);
247 		dev_err(dev->dev, "Failed to request IRQ\n");
252 	ret = of_reserved_mem_device_init(dev->dev);
254 		dev_err(dev->dev, "Failed to reserve memory\n");
259 	ret = sunxi_sram_claim(dev->dev);
261 		dev_err(dev->dev, "Failed to claim SRAM\n");
266 	dev->ahb_clk = devm_clk_get(dev->dev, "ahb");
267 	if (IS_ERR(dev->ahb_clk)) {
268 		dev_err(dev->dev, "Failed to get AHB clock\n");
270 		ret = PTR_ERR(dev->ahb_clk);
274 	dev->mod_clk = devm_clk_get(dev->dev, "mod");
275 	if (IS_ERR(dev->mod_clk)) {
276 		dev_err(dev->dev, "Failed to get MOD clock\n");
278 		ret = PTR_ERR(dev->mod_clk);
282 	dev->ram_clk = devm_clk_get(dev->dev, "ram");
283 	if (IS_ERR(dev->ram_clk)) {
284 		dev_err(dev->dev, "Failed to get RAM clock\n");
286 		ret = PTR_ERR(dev->ram_clk);
290 	dev->rstc = devm_reset_control_get(dev->dev, NULL);
291 	if (IS_ERR(dev->rstc)) {
292 		dev_err(dev->dev, "Failed to get reset control\n");
294 		ret = PTR_ERR(dev->rstc);
298 	dev->base = devm_platform_ioremap_resource(dev->pdev, 0);
299 	if (IS_ERR(dev->base)) {
300 		dev_err(dev->dev, "Failed to map registers\n");
302 		ret = PTR_ERR(dev->base);
306 	ret = clk_set_rate(dev->mod_clk, variant->mod_rate);
308 		dev_err(dev->dev, "Failed to set clock rate\n");
313 	pm_runtime_enable(dev->dev);
314 	if (!pm_runtime_enabled(dev->dev)) {
315 		ret = cedrus_hw_resume(dev->dev);
323 	pm_runtime_disable(dev->dev);
325 	sunxi_sram_release(dev->dev);
327 	of_reserved_mem_device_release(dev->dev);
332 void cedrus_hw_remove(struct cedrus_dev *dev)
334 	pm_runtime_disable(dev->dev);
335 	if (!pm_runtime_status_suspended(dev->dev))
336 		cedrus_hw_suspend(dev->dev);
338 	sunxi_sram_release(dev->dev);
340 	of_reserved_mem_device_release(dev->dev);