sunxi/cedrus/cedrus_h265.c

76 	cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK);
86 	cedrus_write(dev, VE_DEC_H265_CTRL, reg);
91 	cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset);
100 		cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++);
247 		cedrus_write(dev, VE_DEC_H265_TRIGGER,
260 	cedrus_write(dev, VE_DEC_H265_TRIGGER,
279 	cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF0,
285 	cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF1,
300 				cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
310 				cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
320 				cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
329 			cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
389 	cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0));
390 	cedrus_write(dev, VE_DEC_H265_TILE_END_CTB,
492 	cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0);
495 	cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg);
506 	cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg);
509 	cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
516 	cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
522 		cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
523 		cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
528 		cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);
531 	cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC);
564 	cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg);
597 	cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg);
611 	cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg);
636 	cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg);
666 	cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg);
709 	cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg);
728 	cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg);
736 	cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg);
738 	cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR,
746 	cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg);
756 	cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg);
760 	cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg);
777 	cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index);
822 		cedrus_write(dev, VE_DEC_H265_OFFSET_ADDR_FIRST_OUT, reg);
825 		cedrus_write(dev, VE_DEC_H265_10BIT_CONFIGURE, reg);
829 	cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK);
902 	cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE);