Lines Matching refs:isc
21 #include <linux/atmel-isc-media.h>
32 #include "atmel-isc-regs.h"
33 #include "atmel-isc.h"
51 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
53 struct isc_ctrls *ctrls = &isc->ctrls;
56 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
57 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
58 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
59 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
61 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
62 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
63 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
64 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
67 static inline void isc_update_awb_ctrls(struct isc_device *isc)
69 struct isc_ctrls *ctrls = &isc->ctrls;
73 regmap_write(isc->regmap, ISC_WB_O_RGR,
76 regmap_write(isc->regmap, ISC_WB_O_BGB,
79 regmap_write(isc->regmap, ISC_WB_G_RGR,
82 regmap_write(isc->regmap, ISC_WB_G_BGB,
87 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
93 isc->ctrls.gain[c] = 1 << 9;
95 isc->ctrls.offset[c] = 0;
104 struct isc_device *isc = vb2_get_drv_priv(vq);
105 unsigned int size = isc->fmt.fmt.pix.sizeimage;
119 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
120 unsigned long size = isc->fmt.fmt.pix.sizeimage;
123 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
130 vbuf->field = isc->fmt.fmt.pix.field;
135 static void isc_crop_pfe(struct isc_device *isc)
137 struct regmap *regmap = isc->regmap;
140 h = isc->fmt.fmt.pix.height;
141 w = isc->fmt.fmt.pix.width;
149 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
174 static void isc_start_dma(struct isc_device *isc)
176 struct regmap *regmap = isc->regmap;
177 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
181 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
182 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
184 switch (isc->config.fourcc) {
186 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
188 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
192 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
194 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
201 dctrl_dview = isc->config.dctrl_dview;
203 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
205 spin_lock(&isc->awb_lock);
207 spin_unlock(&isc->awb_lock);
210 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
212 struct regmap *regmap = isc->regmap;
213 struct isc_ctrls *ctrls = &isc->ctrls;
221 regmap_field_write(isc->pipeline[i], val);
227 bay_cfg = isc->config.sd_format->cfa_baycfg;
230 isc_update_awb_ctrls(isc);
231 isc_update_v4l2_ctrls(isc);
235 gamma = &isc->gamma_table[ctrls->gamma_index][0];
240 isc->config_dpc(isc);
241 isc->config_csc(isc);
242 isc->config_cbc(isc);
243 isc->config_cc(isc);
244 isc->config_gam(isc);
247 static int isc_update_profile(struct isc_device *isc)
249 struct regmap *regmap = isc->regmap;
262 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
269 static void isc_set_histogram(struct isc_device *isc, bool enable)
271 struct regmap *regmap = isc->regmap;
272 struct isc_ctrls *ctrls = &isc->ctrls;
275 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
277 (isc->config.sd_format->cfa_baycfg
280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
284 isc_update_profile(isc);
290 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
297 static int isc_configure(struct isc_device *isc)
299 struct regmap *regmap = isc->regmap;
301 struct isc_subdev_entity *subdev = isc->current_subdev;
303 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
304 pipeline = isc->config.bits_pipeline;
306 dcfg = isc->config.dcfg_imode | isc->dcfg;
316 isc->config_rlp(isc);
318 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
321 isc_set_pipeline(isc, pipeline);
327 if (isc->ctrls.awb &&
328 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
329 isc_set_histogram(isc, true);
331 isc_set_histogram(isc, false);
334 return isc_update_profile(isc);
339 struct isc_device *isc = vb2_get_drv_priv(vq);
340 struct regmap *regmap = isc->regmap;
346 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
348 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
353 ret = pm_runtime_resume_and_get(isc->dev);
355 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
360 ret = isc_configure(isc);
367 spin_lock_irqsave(&isc->dma_queue_lock, flags);
369 isc->sequence = 0;
370 isc->stop = false;
371 reinit_completion(&isc->comp);
373 isc->cur_frm = list_first_entry(&isc->dma_queue,
375 list_del(&isc->cur_frm->list);
377 isc_crop_pfe(isc);
378 isc_start_dma(isc);
380 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
383 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
384 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
389 pm_runtime_put_sync(isc->dev);
391 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
394 spin_lock_irqsave(&isc->dma_queue_lock, flags);
395 list_for_each_entry(buf, &isc->dma_queue, list)
397 INIT_LIST_HEAD(&isc->dma_queue);
398 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
405 struct isc_device *isc = vb2_get_drv_priv(vq);
410 mutex_lock(&isc->awb_mutex);
411 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
413 isc->stop = true;
416 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
417 v4l2_err(&isc->v4l2_dev,
420 mutex_unlock(&isc->awb_mutex);
423 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
425 pm_runtime_put_sync(isc->dev);
428 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
430 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
433 spin_lock_irqsave(&isc->dma_queue_lock, flags);
434 if (unlikely(isc->cur_frm)) {
435 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
437 isc->cur_frm = NULL;
439 list_for_each_entry(buf, &isc->dma_queue, list)
441 INIT_LIST_HEAD(&isc->dma_queue);
442 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
449 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
452 spin_lock_irqsave(&isc->dma_queue_lock, flags);
453 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
455 isc->cur_frm = buf;
456 isc_start_dma(isc);
458 list_add_tail(&buf->list, &isc->dma_queue);
459 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
462 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
465 unsigned int num_formats = isc->num_user_formats;
470 fmt = isc->user_formats[i];
491 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
500 struct isc_device *isc = video_drvdata(file);
504 if (index < isc->controller_formats_size) {
505 f->pixelformat = isc->controller_formats[index].fourcc;
509 index -= isc->controller_formats_size;
513 for (i = 0; i < isc->formats_list_size; i++) {
514 if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
515 !isc->formats_list[i].sd_support)
518 f->pixelformat = isc->formats_list[i].fourcc;
530 struct isc_device *isc = video_drvdata(file);
532 *fmt = isc->fmt;
541 static int isc_try_validate_formats(struct isc_device *isc)
547 switch (isc->try_config.fourcc) {
591 v4l2_dbg(1, debug, &isc->v4l2_dev,
596 if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
600 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
601 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
612 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
614 isc->try_config.rlp_cfg_mode = 0;
616 switch (isc->try_config.fourcc) {
621 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
622 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
623 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
624 isc->try_config.bpp = 8;
625 isc->try_config.bpp_v4l2 = 8;
631 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
632 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
633 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
634 isc->try_config.bpp = 16;
635 isc->try_config.bpp_v4l2 = 16;
641 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
642 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
643 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
644 isc->try_config.bpp = 16;
645 isc->try_config.bpp_v4l2 = 16;
648 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
649 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
650 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
651 isc->try_config.bpp = 16;
652 isc->try_config.bpp_v4l2 = 16;
655 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
656 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
657 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
658 isc->try_config.bpp = 16;
659 isc->try_config.bpp_v4l2 = 16;
662 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
663 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
664 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
665 isc->try_config.bpp = 16;
666 isc->try_config.bpp_v4l2 = 16;
670 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
671 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
672 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
673 isc->try_config.bpp = 32;
674 isc->try_config.bpp_v4l2 = 32;
677 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
678 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
679 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
680 isc->try_config.bpp = 12;
681 isc->try_config.bpp_v4l2 = 8; /* only first plane */
684 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
685 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
686 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
687 isc->try_config.bpp = 16;
688 isc->try_config.bpp_v4l2 = 8; /* only first plane */
691 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
692 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
693 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
694 isc->try_config.bpp = 16;
695 isc->try_config.bpp_v4l2 = 16;
698 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
699 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
700 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
701 isc->try_config.bpp = 16;
702 isc->try_config.bpp_v4l2 = 16;
705 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
706 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
707 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
708 isc->try_config.bpp = 16;
709 isc->try_config.bpp_v4l2 = 16;
712 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
713 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
714 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
715 isc->try_config.bpp = 8;
716 isc->try_config.bpp_v4l2 = 8;
719 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
722 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
723 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
724 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
725 isc->try_config.bpp = 16;
726 isc->try_config.bpp_v4l2 = 16;
733 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
734 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
735 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
746 static int isc_try_configure_pipeline(struct isc_device *isc)
748 switch (isc->try_config.fourcc) {
755 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
756 isc->try_config.bits_pipeline = CFA_ENABLE |
760 isc->try_config.bits_pipeline = 0x0;
765 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
766 isc->try_config.bits_pipeline = CFA_ENABLE |
771 isc->try_config.bits_pipeline = 0x0;
776 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
777 isc->try_config.bits_pipeline = CFA_ENABLE |
781 isc->try_config.bits_pipeline = 0x0;
788 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
789 isc->try_config.bits_pipeline = CFA_ENABLE |
793 isc->try_config.bits_pipeline = 0x0;
799 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
800 isc->try_config.bits_pipeline = CFA_ENABLE |
804 isc->try_config.bits_pipeline = 0x0;
808 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
809 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
811 isc->try_config.bits_pipeline = 0x0;
815 isc->adapt_pipeline(isc);
820 static void isc_try_fse(struct isc_device *isc,
834 if (!isc->try_config.sd_format)
837 fse.code = isc->try_config.sd_format->mbus_code;
839 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
846 try_crop->width = isc->max_width;
847 try_crop->height = isc->max_height;
854 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
875 for (i = 0; i < isc->num_user_formats; i++) {
876 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
877 sd_fmt = isc->user_formats[i];
884 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
907 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
908 v4l2_dbg(1, debug, &isc->v4l2_dev,
919 v4l2_dbg(1, debug, &isc->v4l2_dev,
924 isc->try_config.sd_format = sd_fmt;
927 if (pixfmt->width > isc->max_width)
928 pixfmt->width = isc->max_width;
929 if (pixfmt->height > isc->max_height)
930 pixfmt->height = isc->max_height;
942 isc->try_config.fourcc = pixfmt->pixelformat;
944 if (isc_try_validate_formats(isc)) {
945 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
947 ret = isc_try_validate_formats(isc);
952 ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
956 ret = isc_try_configure_pipeline(isc);
961 isc_try_fse(isc, &pad_state);
964 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
972 if (pixfmt->width > isc->max_width)
973 pixfmt->width = isc->max_width;
974 if (pixfmt->height > isc->max_height)
975 pixfmt->height = isc->max_height;
978 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
979 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
988 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
990 memset(&isc->try_config, 0, sizeof(isc->try_config));
995 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1003 ret = isc_try_fmt(isc, f, &mbus_code);
1008 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1014 if (f->fmt.pix.width > isc->max_width)
1015 f->fmt.pix.width = isc->max_width;
1016 if (f->fmt.pix.height > isc->max_height)
1017 f->fmt.pix.height = isc->max_height;
1019 isc->fmt = *f;
1021 if (isc->try_config.sd_format && isc->config.sd_format &&
1022 isc->try_config.sd_format != isc->config.sd_format) {
1023 isc->ctrls.hist_stat = HIST_INIT;
1024 isc_reset_awb_ctrls(isc);
1025 isc_update_v4l2_ctrls(isc);
1028 isc->config = isc->try_config;
1030 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1038 struct isc_device *isc = video_drvdata(file);
1040 if (vb2_is_busy(&isc->vb2_vidq))
1043 return isc_set_fmt(isc, f);
1049 struct isc_device *isc = video_drvdata(file);
1051 return isc_try_fmt(isc, f, NULL);
1084 struct isc_device *isc = video_drvdata(file);
1086 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1091 struct isc_device *isc = video_drvdata(file);
1093 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1099 struct isc_device *isc = video_drvdata(file);
1106 for (i = 0; i < isc->num_user_formats; i++)
1107 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1110 for (i = 0; i < isc->controller_formats_size; i++)
1111 if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1120 fsize->stepwise.max_width = isc->max_width;
1122 fsize->stepwise.max_height = isc->max_height;
1161 struct isc_device *isc = video_drvdata(file);
1162 struct v4l2_subdev *sd = isc->current_subdev->sd;
1165 if (mutex_lock_interruptible(&isc->lock))
1181 ret = isc_set_fmt(isc, &isc->fmt);
1188 mutex_unlock(&isc->lock);
1194 struct isc_device *isc = video_drvdata(file);
1195 struct v4l2_subdev *sd = isc->current_subdev->sd;
1199 mutex_lock(&isc->lock);
1208 mutex_unlock(&isc->lock);
1225 struct isc_device *isc = (struct isc_device *)dev_id;
1226 struct regmap *regmap = isc->regmap;
1236 spin_lock(&isc->dma_queue_lock);
1237 if (isc->cur_frm) {
1238 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1242 vbuf->sequence = isc->sequence++;
1244 isc->cur_frm = NULL;
1247 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1248 isc->cur_frm = list_first_entry(&isc->dma_queue,
1250 list_del(&isc->cur_frm->list);
1252 isc_start_dma(isc);
1255 if (isc->stop)
1256 complete(&isc->comp);
1259 spin_unlock(&isc->dma_queue_lock);
1263 schedule_work(&isc->awb_work);
1271 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1273 struct regmap *regmap = isc->regmap;
1274 struct isc_ctrls *ctrls = &isc->ctrls;
1282 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1301 v4l2_dbg(1, debug, &isc->v4l2_dev,
1302 "isc wb: hist_id %u, hist_count %u",
1308 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1325 v4l2_dbg(1, debug, &isc->v4l2_dev,
1326 "isc wb: green components average %llu\n", avg);
1380 v4l2_dbg(1, debug, &isc->v4l2_dev,
1381 "isc wb: component %d, s_gain %u, gw_gain %u\n",
1390 v4l2_dbg(1, debug, &isc->v4l2_dev,
1391 "isc wb: component %d, final gain %u\n",
1398 struct isc_device *isc =
1400 struct regmap *regmap = isc->regmap;
1401 struct isc_ctrls *ctrls = &isc->ctrls;
1411 isc_hist_count(isc, &min, &max);
1413 v4l2_dbg(1, debug, &isc->v4l2_dev,
1414 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1427 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1429 ret = pm_runtime_resume_and_get(isc->dev);
1444 spin_lock_irqsave(&isc->awb_lock, flags);
1445 isc_update_awb_ctrls(isc);
1446 spin_unlock_irqrestore(&isc->awb_lock, flags);
1453 v4l2_info(&isc->v4l2_dev,
1456 isc_update_v4l2_ctrls(isc);
1460 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1468 mutex_lock(&isc->awb_mutex);
1471 if (isc->stop) {
1472 mutex_unlock(&isc->awb_mutex);
1476 isc_update_profile(isc);
1478 mutex_unlock(&isc->awb_mutex);
1484 pm_runtime_put_sync(isc->dev);
1489 struct isc_device *isc = container_of(ctrl->handler,
1491 struct isc_ctrls *ctrls = &isc->ctrls;
1519 struct isc_device *isc = container_of(ctrl->handler,
1521 struct isc_ctrls *ctrls = &isc->ctrls;
1535 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1537 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1539 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1541 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1544 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1546 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1548 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1550 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1552 isc_update_awb_ctrls(isc);
1554 mutex_lock(&isc->awb_mutex);
1555 if (vb2_is_streaming(&isc->vb2_vidq)) {
1560 isc_update_profile(isc);
1567 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1569 mutex_unlock(&isc->awb_mutex);
1573 vb2_is_streaming(&isc->vb2_vidq) &&
1574 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1575 isc_set_histogram(isc, true);
1586 isc_set_histogram(isc, true);
1587 v4l2_dbg(1, debug, &isc->v4l2_dev,
1597 struct isc_device *isc = container_of(ctrl->handler,
1599 struct isc_ctrls *ctrls = &isc->ctrls;
1667 static int isc_ctrl_init(struct isc_device *isc)
1670 struct isc_ctrls *ctrls = &isc->ctrls;
1675 isc_reset_awb_ctrls(isc);
1682 isc->config_ctrls(isc, ops);
1687 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1688 isc->gamma_max);
1689 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1694 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1698 if (!isc->do_wb_ctrl) {
1704 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1706 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1707 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1708 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1709 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1710 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1711 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1712 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1713 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1719 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1730 struct isc_device *isc = container_of(notifier->v4l2_dev,
1735 if (video_is_registered(&isc->video_dev)) {
1736 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1749 struct isc_device *isc = container_of(notifier->v4l2_dev,
1751 mutex_destroy(&isc->awb_mutex);
1752 cancel_work_sync(&isc->awb_work);
1753 video_unregister_device(&isc->video_dev);
1754 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1757 static struct isc_format *find_format_by_code(struct isc_device *isc,
1760 struct isc_format *fmt = &isc->formats_list[0];
1763 for (i = 0; i < isc->formats_list_size; i++) {
1775 static int isc_formats_init(struct isc_device *isc)
1778 struct v4l2_subdev *subdev = isc->current_subdev->sd;
1780 u32 list_size = isc->formats_list_size;
1790 fmt = find_format_by_code(isc, mbus_code.code, &i);
1792 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
1804 isc->num_user_formats = num_fmts;
1805 isc->user_formats = devm_kcalloc(isc->dev,
1806 num_fmts, sizeof(*isc->user_formats),
1808 if (!isc->user_formats)
1811 fmt = &isc->formats_list[0];
1814 isc->user_formats[j++] = fmt;
1821 static int isc_set_default_fmt(struct isc_device *isc)
1829 .pixelformat = isc->user_formats[0]->fourcc,
1834 ret = isc_try_fmt(isc, &f, NULL);
1838 isc->fmt = f;
1844 struct isc_device *isc = container_of(notifier->v4l2_dev,
1846 struct video_device *vdev = &isc->video_dev;
1847 struct vb2_queue *q = &isc->vb2_vidq;
1850 INIT_WORK(&isc->awb_work, isc_awb_work);
1852 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1854 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
1858 isc->current_subdev = container_of(notifier,
1860 mutex_init(&isc->lock);
1861 mutex_init(&isc->awb_mutex);
1863 init_completion(&isc->comp);
1868 q->drv_priv = isc;
1873 q->lock = &isc->lock;
1875 q->dev = isc->dev;
1879 v4l2_err(&isc->v4l2_dev,
1885 INIT_LIST_HEAD(&isc->dma_queue);
1886 spin_lock_init(&isc->dma_queue_lock);
1887 spin_lock_init(&isc->awb_lock);
1889 ret = isc_formats_init(isc);
1891 v4l2_err(&isc->v4l2_dev,
1896 ret = isc_set_default_fmt(isc);
1898 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
1902 ret = isc_ctrl_init(isc);
1904 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
1913 vdev->v4l2_dev = &isc->v4l2_dev;
1916 vdev->lock = &isc->lock;
1917 vdev->ctrl_handler = &isc->ctrls.handler;
1919 video_set_drvdata(vdev, isc);
1923 v4l2_err(&isc->v4l2_dev,
1931 mutex_destroy(&isc->awb_mutex);
1932 mutex_destroy(&isc->lock);
1943 void atmel_isc_subdev_cleanup(struct isc_device *isc)
1947 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1952 INIT_LIST_HEAD(&isc->subdev_entities);
1956 int atmel_isc_pipeline_init(struct isc_device *isc)
1958 struct device *dev = isc->dev;
1959 struct regmap *regmap = isc->regmap;
1979 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1980 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1981 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1982 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1990 isc->pipeline[i] = regs;