atomisp/pci/sh_css_sp.c

117 		    unsigned int stage)
125 		    sh_css_store_isp_stage_to_ddr(pipe_num, stage);
126 	sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] =
127 	    sh_css_store_sp_stage_to_ddr(pipe_num, stage);
770 is_sp_stage(struct ia_css_pipeline_stage *stage)
772 	assert(stage);
773 	return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC;
878 		     unsigned int stage,
916 		sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL;
923 		sh_css_sp_stage.deinterleaved = ((stage == 0) && continuous);
928 	 * the stage type.
931 	sh_css_sp_stage.num		= (uint8_t)stage;
972 	 * Even when a stage does not need uds and does not params,
1042 sp_init_stage(struct ia_css_pipeline_stage *stage,
1072 	 * Best is to allocate it at stage creation time together with host
1079 	assert(stage);
1081 	binary = stage->binary;
1082 	firmware = stage->firmware;
1083 	args = &stage->args;
1084 	stage_num = stage->stage_num;
1112 		/* SP stage */
1113 		assert(stage->sp_func != IA_CSS_PIPELINE_NO_FUNC);
1137 sp_init_sp_stage(struct ia_css_pipeline_stage *stage,
1143 	const struct sh_css_binary_args *args = &stage->args;
1145 	assert(stage);
1146 	switch (stage->sp_func) {
1150 					 stage->max_input_width,
1158 					  pipe_num, stage->max_input_width, if_config_index);
1181 	/* Get first stage */
1182 	struct ia_css_pipeline_stage *stage        = NULL;
1214 	for (stage = me->stages, num = 0; stage; stage = stage->next, num++) {
1215 		stage->stage_num = num;
1216 		ia_css_debug_pipe_graph_dump_stage(stage, id);
1231 	/* Init stage data */
1289 	for (stage = me->stages, num = 0; stage; stage = stage->next, num++) {
1291 		if (is_sp_stage(stage)) {
1292 			sp_init_sp_stage(stage, pipe_num, two_ppc,
1295 			if ((stage->stage_num != 0) ||
1300 			sp_init_stage(stage, pipe_num,
1359  * These have a pipeline of just 1 stage.