atomisp/pci/ia_css_isp_params.c

72     const struct ia_css_pipeline_stage *stage,
76 	    stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
78 	    stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
82 						  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset];
92     const struct ia_css_pipeline_stage *stage,
99 		    stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
102 		    stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
109 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
113 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
127     const struct ia_css_pipeline_stage *stage,
134 		    stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
137 		    stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
144 						&stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
148 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
162     const struct ia_css_pipeline_stage *stage,
169 		    stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
172 		    stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
178 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
182 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
190 		    stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
196 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] =
209     const struct ia_css_pipeline_stage *stage,
216 		    stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
219 		    stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
226 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
230 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
244     const struct ia_css_pipeline_stage *stage,
251 		    stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
254 		    stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
261 					   &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
265 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
279     const struct ia_css_pipeline_stage *stage,
286 		    stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
289 		    stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
296 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
300 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
314     const struct ia_css_pipeline_stage *stage,
321 		    stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
324 		    stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
330 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
334 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
347     const struct ia_css_pipeline_stage *stage,
354 		    stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
357 		    stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
364 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
368 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
382     const struct ia_css_pipeline_stage *stage,
389 		    stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
392 		    stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
398 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
402 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
415     const struct ia_css_pipeline_stage *stage,
422 		    stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
425 		    stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
432 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
436 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
450     const struct ia_css_pipeline_stage *stage,
457 		    stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
460 		    stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
467 					      &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
471 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
485     const struct ia_css_pipeline_stage *stage,
492 		    stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
495 		    stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
502 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
506 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
520     const struct ia_css_pipeline_stage *stage,
527 		    stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
530 		    stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
536 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
540 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
548 		    stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
551 		    stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
557 					       &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset],
561 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] =
574     const struct ia_css_pipeline_stage *stage,
581 		    stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
584 		    stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
590 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
594 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
607     const struct ia_css_pipeline_stage *stage,
614 		    stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
617 		    stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
624 					      &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
628 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
642     const struct ia_css_pipeline_stage *stage,
649 		    stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
652 		    stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
659 					      &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
663 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
677     const struct ia_css_pipeline_stage *stage,
684 		    stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
687 		    stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
694 						    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset],
698 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] =
712     const struct ia_css_pipeline_stage *stage,
719 		    stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
722 		    stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
729 						    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset],
733 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] =
747     const struct ia_css_pipeline_stage *stage,
754 		    stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
757 		    stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
764 						    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset],
768 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] =
782     const struct ia_css_pipeline_stage *stage,
789 		    stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
792 		    stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
801 			    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset];
806 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
820     const struct ia_css_pipeline_stage *stage,
827 		    stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
830 		    stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
837 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
841 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
855     const struct ia_css_pipeline_stage *stage,
862 		    stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
865 		    stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
872 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
876 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
890     const struct ia_css_pipeline_stage *stage,
897 		    stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
900 		    stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
906 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
910 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
918 		    stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
921 		    stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
927 					      &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
931 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
944     const struct ia_css_pipeline_stage *stage,
951 		    stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
954 		    stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
961 					     &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
965 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
979     const struct ia_css_pipeline_stage *stage,
986 		    stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
989 		    stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
995 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
999 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1012     const struct ia_css_pipeline_stage *stage,
1019 		    stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
1022 		    stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
1031 			    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset];
1035 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1049     const struct ia_css_pipeline_stage *stage,
1056 		    stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
1059 		    stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
1066 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1070 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1084     const struct ia_css_pipeline_stage *stage,
1091 		    stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
1094 		    stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
1101 					   &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1105 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1119     const struct ia_css_pipeline_stage *stage,
1126 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
1129 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
1136 							 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
1140 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
1154     const struct ia_css_pipeline_stage *stage,
1161 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
1164 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
1171 							 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
1175 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
1189     const struct ia_css_pipeline_stage *stage,
1196 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
1199 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
1206 						    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1210 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1224     const struct ia_css_pipeline_stage *stage,
1231 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
1234 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
1241 						    &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1245 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1259     const struct ia_css_pipeline_stage *stage,
1266 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
1269 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
1276 							  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
1280 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
1294     const struct ia_css_pipeline_stage *stage,
1301 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
1304 		    stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
1311 							  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset],
1315 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] =
1329     const struct ia_css_pipeline_stage *stage,
1336 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
1339 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
1346 						     &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1350 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1364     const struct ia_css_pipeline_stage *stage,
1371 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
1374 		    stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
1381 						     &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1385 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1399     const struct ia_css_pipeline_stage *stage,
1406 		    stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
1409 		    stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
1415 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1419 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1432     const struct ia_css_pipeline_stage *stage,
1439 		    stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
1442 		    stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
1448 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1452 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1465     const struct ia_css_pipeline_stage *stage,
1472 		    stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
1475 		    stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
1482 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1486 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1500     const struct ia_css_pipeline_stage *stage,
1507 		    stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
1510 		    stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
1517 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1521 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1535     const struct ia_css_pipeline_stage *stage,
1542 		    stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
1545 		    stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
1551 					 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1555 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1568     const struct ia_css_pipeline_stage *stage,
1575 		    stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
1578 		    stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
1585 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1589 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1598 		    stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
1601 		    stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
1608 						&stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset],
1612 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] =
1626     const struct ia_css_pipeline_stage *stage,
1633 		    stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
1636 		    stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
1643 						      &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset],
1647 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] =
1661     const struct ia_css_pipeline_stage *stage,
1668 		    stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
1671 		    stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
1678 					  &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1682 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1696     const struct ia_css_pipeline_stage *stage,
1703 		    stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
1706 		    stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
1713 					   &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
1717 			params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] =
1730     const struct ia_css_pipeline_stage *stage,