hive_isp_css_common/host/irq.c

25     const irq_ID_t		ID);
28     const irq_ID_t				ID);
60     const irq_ID_t				ID)
64 	assert(ID < N_IRQ_ID);
65 	assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH);
67 	if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) {
68 		mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]);
71 	irq_reg_store(ID,
80     const irq_ID_t				ID,
83 	unsigned int mask = irq_reg_load(ID,
85 	unsigned int enable = irq_reg_load(ID,
87 	unsigned int edge_in = irq_reg_load(ID,
91 	assert(ID < N_IRQ_ID);
92 	assert(irq_id < IRQ_N_CHANNEL[ID]);
101 	irq_reg_store(ID,
104 	irq_reg_store(ID,
107 	irq_reg_store(ID,
110 	irq_reg_store(ID,
113 	irq_reg_store(ID,
116 	irq_wait_for_write_complete(ID);
122     const irq_ID_t	ID,
131 	irq_reg_store(ID,
137     const irq_ID_t				ID,
140 	unsigned int mask = irq_reg_load(ID,
142 	unsigned int enable = irq_reg_load(ID,
146 	assert(ID < N_IRQ_ID);
147 	assert(irq_id < IRQ_N_CHANNEL[ID]);
153 	irq_reg_store(ID,
156 	irq_reg_store(ID,
159 	irq_reg_store(ID,
162 	irq_wait_for_write_complete(ID);
168     const irq_ID_t				ID,
171 	unsigned int irq_status = irq_reg_load(ID,
176 	assert(ID < N_IRQ_ID);
180 	for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) {
184 	if (idx == IRQ_N_CHANNEL[ID])
191 	irq_reg_store(ID,
194 	irq_wait_for_write_complete(ID);
208     const irq_ID_t				ID,
213 	OP___assert(ID == IRQ0_ID);
214 	OP___assert(IRQ_BASE[ID] != (hrt_address)-1);
217 	(void)ID;
242 	irq_ID_t		ID = virq_get_irq_id(irq_ID, &channel_ID);
244 	assert(ID < N_IRQ_ID);
252 		irq_enable_channel(ID, channel_ID);
253 		if (IRQ_NESTING_ID[ID] != N_virq_id) {
255 			irq_enable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]);
258 		irq_disable_channel(ID, channel_ID);
259 		if ((IRQ_NESTING_ID[ID] != N_virq_id) && !any_irq_channel_enabled(ID)) {
261 			irq_disable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]);
281 	irq_ID_t ID;
285 	for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
286 		if (any_irq_channel_enabled(ID)) {
287 			hrt_data	irq_data = irq_reg_load(ID,
295 			irq_info->irq_status_reg[ID] |= irq_data;
297 			irq_reg_store(ID,
300 			irq_wait_for_write_complete(ID);
309 	irq_ID_t ID;
313 	for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
314 		irq_info->irq_status_reg[ID] = 0;
326 	irq_ID_t ID;
346 	for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) {
347 		if (IRQ_NESTING_ID[ID] == (enum virq_id)idx) {
353 	if (ID != IRQ0_ID) {
354 		irq_status = irq_reg_load(ID,
357 		for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) {
362 		if (idx == IRQ_N_CHANNEL[ID]) {
372 				      _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << IRQ_NESTING_ID[ID]);
374 	} /* if (ID != IRQ0_ID) */
377 	irq_reg_store(ID,
380 	irq_wait_for_write_complete(ID);
382 	idx += IRQ_N_ID_OFFSET[ID];
390     const irq_ID_t		ID)
392 	assert(ID < N_IRQ_ID);
393 	assert(IRQ_BASE[ID] != (hrt_address)-1);
394 	(void)ia_css_device_load_uint32(IRQ_BASE[ID] +
399     const irq_ID_t				ID)
403 	assert(ID < N_IRQ_ID);
405 	en_reg = irq_reg_load(ID,
415 	irq_ID_t ID;
419 	for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
420 		if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) {
425 	*channel_ID = (unsigned int)irq_ID - IRQ_N_ID_OFFSET[ID];
427 	return ID;