Lines Matching defs:ID

33     const pixelgen_ID_t ID,
36 assert(ID < N_PIXELGEN_ID);
37 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1);
38 return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(
47 const pixelgen_ID_t ID,
51 assert(ID < N_PIXELGEN_ID);
52 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
54 ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data),
70 const pixelgen_ID_t ID,
74 pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
76 pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX);
78 pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX);
80 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX);
82 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX);
84 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX);
86 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX);
88 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX);
90 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX);
92 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX);
94 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX);
96 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX);
98 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX);
100 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX);
102 pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX);
104 pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX);
106 pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX);
108 pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX);
110 pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX);
112 pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX);
114 pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX);
116 pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX);
118 pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX);
120 pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX);
122 pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX);
124 pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX);
126 pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
134 const pixelgen_ID_t ID,
137 ia_css_print("Pixel Generator ID %d Enable 0x%x\n", ID, state->com_enable);
138 ia_css_print("Pixel Generator ID %d PRBS reset value 0 0x%x\n", ID,
140 ia_css_print("Pixel Generator ID %d PRBS reset value 1 0x%x\n", ID,
142 ia_css_print("Pixel Generator ID %d SYNC SID 0x%x\n", ID, state->syng_sid);
143 ia_css_print("Pixel Generator ID %d syng free run 0x%x\n", ID,
145 ia_css_print("Pixel Generator ID %d syng pause 0x%x\n", ID, state->syng_pause);
146 ia_css_print("Pixel Generator ID %d syng no of frames 0x%x\n", ID,
148 ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x\n", ID,
150 ia_css_print("Pixel Generator ID %d syng no of line 0x%x\n", ID,
152 ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x\n", ID,
154 ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x\n", ID,
156 ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x\n", ID,
158 ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x\n", ID,
160 ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x\n", ID,
162 ia_css_print("Pixel Generator ID %d syng stat done 0x%x\n", ID,
164 ia_css_print("Pixel Generator ID %d tpg mode 0x%x\n", ID, state->tpg_mode);
165 ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID,
167 ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID,
169 ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x\n", ID,
171 ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x\n", ID,
173 ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x\n", ID,
175 ia_css_print("Pixel Generator ID %d tpg r1 0x%x\n", ID, state->tpg_r1);
176 ia_css_print("Pixel Generator ID %d tpg g1 0x%x\n", ID, state->tpg_g1);
177 ia_css_print("Pixel Generator ID %d tpg b1 0x%x\n", ID, state->tpg_b1);
178 ia_css_print("Pixel Generator ID %d tpg r2 0x%x\n", ID, state->tpg_r2);
179 ia_css_print("Pixel Generator ID %d tpg g2 0x%x\n", ID, state->tpg_g2);
180 ia_css_print("Pixel Generator ID %d tpg b2 0x%x\n", ID, state->tpg_b2);