css_2401_system/host/csi_rx_private.h

38     const csi_rx_frontend_ID_t ID,
41 	assert(ID < N_CSI_RX_FRONTEND_ID);
42 	assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
43 	return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(
52     const csi_rx_frontend_ID_t ID,
56 	assert(ID < N_CSI_RX_FRONTEND_ID);
57 	assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
59 	ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
68     const csi_rx_backend_ID_t ID,
71 	assert(ID < N_CSI_RX_BACKEND_ID);
72 	assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
73 	return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(
82     const csi_rx_backend_ID_t ID,
86 	assert(ID < N_CSI_RX_BACKEND_ID);
87 	assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
89 	ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
105     const csi_rx_frontend_ID_t ID,
110 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
112 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
120     const csi_rx_frontend_ID_t ID,
126 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
128 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX);
130 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX);
132 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX);
134 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX);
136 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX);
138 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX);
140 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX);
146 	for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
148 		    ID,
159     const csi_rx_frontend_ID_t ID,
164 	ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID,
166 	ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID,
168 	ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID,
170 	ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status);
171 	ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID,
173 	ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID,
175 	ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID,
177 	ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID,
184 	for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
185 		ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i,
187 		ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i,
197     const csi_rx_backend_ID_t ID,
203 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
206 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
210 		    csi_rx_be_ctrl_reg_load(ID,
215 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX);
218 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX);
220 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX);
222 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX);
226 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX);
229 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
232 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
235 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX);
238 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX);
240 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX);
245 	for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
247 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i);
249 	for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
251 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i);
260     const csi_rx_backend_ID_t ID,
265 	ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable);
266 	ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status);
270 			     ID, i, state->status);
272 	ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16);
273 	ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18);
274 	ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID,
276 	ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID,
280 		ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i,
285 		     ID, state->global_lut_disregard_reg);
286 	ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID,
292 	for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
293 		ia_css_print("CSI RX BE STATE Controller ID %d Short packet entry %d short packet lut id 0x%x\n",
294 			     ID, i,
297 	for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
298 		ia_css_print("CSI RX BE STATE Controller ID %d Long packet entry %d long packet lut id 0x%x\n",
299 			     ID, i,