iio/frequency/ad9834.c

109 static int ad9834_write_frequency(struct ad9834_state *st,
115 	clk_freq = clk_get_rate(st->mclk);
122 	st->freq_data[0] = cpu_to_be16(addr | (regval &
124 	st->freq_data[1] = cpu_to_be16(addr | ((regval >>
128 	return spi_sync(st->spi, &st->freq_msg);
131 static int ad9834_write_phase(struct ad9834_state *st,
136 	st->data = cpu_to_be16(addr | phase);
138 	return spi_sync(st->spi, &st->msg);
147 	struct ad9834_state *st = iio_priv(indio_dev);
156 	mutex_lock(&st->lock);
160 		ret = ad9834_write_frequency(st, this_attr->address, val);
164 		ret = ad9834_write_phase(st, this_attr->address, val);
167 		if (st->control & AD9834_MODE) {
173 			st->control |= AD9834_OPBITEN;
175 			st->control &= ~AD9834_OPBITEN;
177 		st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
178 		ret = spi_sync(st->spi, &st->msg);
182 			st->control |= AD9834_PIN_SW;
184 			st->control &= ~AD9834_PIN_SW;
185 		st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
186 		ret = spi_sync(st->spi, &st->msg);
191 			st->control &= ~(this_attr->address | AD9834_PIN_SW);
193 			st->control |= this_attr->address;
194 			st->control &= ~AD9834_PIN_SW;
199 		st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
200 		ret = spi_sync(st->spi, &st->msg);
204 			st->control &= ~AD9834_RESET;
206 			st->control |= AD9834_RESET;
208 		st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
209 		ret = spi_sync(st->spi, &st->msg);
214 	mutex_unlock(&st->lock);
225 	struct ad9834_state *st = iio_priv(indio_dev);
228 	bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
230 	mutex_lock(&st->lock);
235 			st->control &= ~AD9834_MODE;
237 				st->control &= ~AD9834_OPBITEN;
240 				st->control &= ~AD9834_OPBITEN;
241 				st->control |= AD9834_MODE;
242 			} else if (st->control & AD9834_OPBITEN) {
245 				st->control |= AD9834_MODE;
248 			st->control &= ~AD9834_MODE;
249 			st->control |= AD9834_OPBITEN;
257 		    !(st->control & AD9834_MODE)) {
258 			st->control &= ~AD9834_MODE;
259 			st->control |= AD9834_OPBITEN;
270 		st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
271 		ret = spi_sync(st->spi, &st->msg);
273 	mutex_unlock(&st->lock);
284 	struct ad9834_state *st = iio_priv(indio_dev);
287 	if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
289 	else if (st->control & AD9834_OPBITEN)
306 	struct ad9834_state *st = iio_priv(indio_dev);
309 	if (st->control & AD9834_MODE)
399 	struct ad9834_state *st;
418 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
423 	st = iio_priv(indio_dev);
424 	mutex_init(&st->lock);
425 	st->mclk = devm_clk_get_enabled(&spi->dev, NULL);
426 	if (IS_ERR(st->mclk)) {
428 		return PTR_ERR(st->mclk);
431 	st->spi = spi;
432 	st->devid = spi_get_device_id(spi)->driver_data;
434 	switch (st->devid) {
447 	st->xfer.tx_buf = &st->data;
448 	st->xfer.len = 2;
450 	spi_message_init(&st->msg);
451 	spi_message_add_tail(&st->xfer, &st->msg);
453 	st->freq_xfer[0].tx_buf = &st->freq_data[0];
454 	st->freq_xfer[0].len = 2;
455 	st->freq_xfer[0].cs_change = 1;
456 	st->freq_xfer[1].tx_buf = &st->freq_data[1];
457 	st->freq_xfer[1].len = 2;
459 	spi_message_init(&st->freq_msg);
460 	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
461 	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
463 	st->control = AD9834_B28 | AD9834_RESET;
464 	st->control |= AD9834_DIV2;
466 	if (st->devid == ID_AD9834)
467 		st->control |= AD9834_SIGN_PIB;
469 	st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
470 	ret = spi_sync(st->spi, &st->msg);
476 	ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
480 	ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
484 	ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
488 	ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);