Lines Matching refs:st

129 static int ad9832_write_frequency(struct ad9832_state *st,
134 if (fout > (clk_get_rate(st->mclk) / 2))
137 regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout);
139 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
142 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
145 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
148 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
152 return spi_sync(st->spi, &st->freq_msg);
155 static int ad9832_write_phase(struct ad9832_state *st,
161 st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
164 st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
168 return spi_sync(st->spi, &st->phase_msg);
175 struct ad9832_state *st = iio_priv(indio_dev);
184 mutex_lock(&st->lock);
188 ret = ad9832_write_frequency(st, this_attr->address, val);
194 ret = ad9832_write_phase(st, this_attr->address, val);
198 st->ctrl_ss &= ~AD9832_SELSRC;
200 st->ctrl_ss |= AD9832_SELSRC;
201 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
202 st->ctrl_ss);
203 ret = spi_sync(st->spi, &st->msg);
207 st->ctrl_fp |= AD9832_FREQ;
209 st->ctrl_fp &= ~AD9832_FREQ;
214 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
215 st->ctrl_fp);
216 ret = spi_sync(st->spi, &st->msg);
224 st->ctrl_fp &= ~AD9832_PHASE(3);
225 st->ctrl_fp |= AD9832_PHASE(val);
227 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
228 st->ctrl_fp);
229 ret = spi_sync(st->spi, &st->msg);
233 st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
236 st->ctrl_src |= AD9832_RESET;
238 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
239 st->ctrl_src);
240 ret = spi_sync(st->spi, &st->msg);
245 mutex_unlock(&st->lock);
306 struct ad9832_state *st;
314 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
318 st = iio_priv(indio_dev);
320 st->avdd = devm_regulator_get(&spi->dev, "avdd");
321 if (IS_ERR(st->avdd))
322 return PTR_ERR(st->avdd);
324 ret = regulator_enable(st->avdd);
330 ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->avdd);
334 st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
335 if (IS_ERR(st->dvdd))
336 return PTR_ERR(st->dvdd);
338 ret = regulator_enable(st->dvdd);
344 ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->dvdd);
348 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
349 if (IS_ERR(st->mclk))
350 return PTR_ERR(st->mclk);
352 st->spi = spi;
353 mutex_init(&st->lock);
361 st->xfer.tx_buf = &st->data;
362 st->xfer.len = 2;
364 spi_message_init(&st->msg);
365 spi_message_add_tail(&st->xfer, &st->msg);
367 st->freq_xfer[0].tx_buf = &st->freq_data[0];
368 st->freq_xfer[0].len = 2;
369 st->freq_xfer[0].cs_change = 1;
370 st->freq_xfer[1].tx_buf = &st->freq_data[1];
371 st->freq_xfer[1].len = 2;
372 st->freq_xfer[1].cs_change = 1;
373 st->freq_xfer[2].tx_buf = &st->freq_data[2];
374 st->freq_xfer[2].len = 2;
375 st->freq_xfer[2].cs_change = 1;
376 st->freq_xfer[3].tx_buf = &st->freq_data[3];
377 st->freq_xfer[3].len = 2;
379 spi_message_init(&st->freq_msg);
380 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
381 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
382 spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
383 spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
385 st->phase_xfer[0].tx_buf = &st->phase_data[0];
386 st->phase_xfer[0].len = 2;
387 st->phase_xfer[0].cs_change = 1;
388 st->phase_xfer[1].tx_buf = &st->phase_data[1];
389 st->phase_xfer[1].len = 2;
391 spi_message_init(&st->phase_msg);
392 spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
393 spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
395 st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
396 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
397 st->ctrl_src);
398 ret = spi_sync(st->spi, &st->msg);
404 ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
408 ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
412 ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
416 ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
420 ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
424 ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);