staging/axis-fifo/axis-fifo.c

124 	void __iomem *base_addr; /* kernel space memory */
158 	iowrite32(tmp, fifo->base_addr + addr_offset);
169 	read_val = ioread32(fifo->base_addr + addr_offset);
323 	iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET);
324 	iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET);
325 	iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET);
329 		  fifo->base_addr + XLLF_IER_OFFSET);
330 	iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET);
368 		if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) {
379 			ioread32(fifo->base_addr + XLLF_RDFO_OFFSET),
394 	bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET);
430 			tmp_buf[i] = ioread32(fifo->base_addr +
507 		if (words_to_write > ioread32(fifo->base_addr +
520 			ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
551 			iowrite32(tmp_buf[i], fifo->base_addr +
561 	iowrite32(ret, fifo->base_addr + XLLF_TLR_OFFSET);
575 		pending_interrupts = ioread32(fifo->base_addr +
577 					      ioread32(fifo->base_addr
587 				  fifo->base_addr + XLLF_ISR_OFFSET);
595 				  fifo->base_addr + XLLF_ISR_OFFSET);
600 				  fifo->base_addr + XLLF_ISR_OFFSET);
605 				  fifo->base_addr + XLLF_ISR_OFFSET);
610 				  fifo->base_addr + XLLF_ISR_OFFSET);
615 				  fifo->base_addr + XLLF_ISR_OFFSET);
620 				  fifo->base_addr + XLLF_ISR_OFFSET);
625 				  fifo->base_addr + XLLF_ISR_OFFSET);
632 				  fifo->base_addr + XLLF_ISR_OFFSET);
639 				  fifo->base_addr + XLLF_ISR_OFFSET);
646 				  fifo->base_addr + XLLF_ISR_OFFSET);
653 				  fifo->base_addr + XLLF_ISR_OFFSET);
660 				  fifo->base_addr + XLLF_ISR_OFFSET);
668 				  fifo->base_addr + XLLF_ISR_OFFSET);
836 	fifo->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
837 	if (IS_ERR(fifo->base_addr)) {
838 		rc = PTR_ERR(fifo->base_addr);
842 	dev_dbg(fifo->dt_device, "remapped memory to 0x%p\n", fifo->base_addr);