drivers/ssb/driver_pcicore.c

19 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
20 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
21 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
22 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
26 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
28 	return ssb_read32(pc->dev, offset);
32 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
34 	ssb_write32(pc->dev, offset, value);
38 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
40 	return ssb_read16(pc->dev, offset);
44 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
46 	ssb_write16(pc->dev, offset, value);
71 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
79 	if (pc->cardbusmode && (dev > 1))
89 		pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
97 		pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
110 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
119 	WARN_ON(!pc->hostmode);
122 	addr = get_cfgspace_addr(pc, bus, dev, func, off);
156 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
165 	WARN_ON(!pc->hostmode);
168 	addr = get_cfgspace_addr(pc, bus, dev, func, off);
320 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
326 	extpci_core = pc;
328 	dev_dbg(pc->dev->dev, "PCIcore in host mode found\n");
332 	pcicore_write32(pc, SSB_PCICORE_CTL, val);
334 	pcicore_write32(pc, SSB_PCICORE_CTL, val);
337 	pcicore_write32(pc, SSB_PCICORE_CTL, val);
339 	pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
342 	if (pc->dev->bus->has_cardbus_slot) {
343 		dev_dbg(pc->dev->dev, "CardBus slot detected\n");
344 		pc->cardbusmode = 1;
346 		ssb_gpio_out(pc->dev->bus, 1, 1);
347 		ssb_gpio_outen(pc->dev->bus, 1, 1);
348 		pcicore_write16(pc, SSB_PCICORE_SPROM(0),
349 				pcicore_read16(pc, SSB_PCICORE_SPROM(0))
354 	pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
357 	pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
360 	pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
375 	ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
378 	ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
381 	pcicore_write32(pc, SSB_PCICORE_IMASK,
397 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
399 	struct ssb_bus *bus = pc->dev->bus;
423 	return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
431 static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
433 	u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
434 	if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
436 		tmp |= (pc->dev->core_index << 12);
437 		pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
441 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
443 	return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
446 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
452 	ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
453 			    ssb_pcicore_polarity_workaround(pc));
454 	tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
456 		ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
459 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
461 	struct ssb_device *pdev = pc->dev;
465 	tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
468 	pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
479 		tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
481 		pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
485 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
488 	u8 rev = pc->dev->id.revision;
492 		tmp = ssb_pcie_read(pc, 0x4);
494 		ssb_pcie_write(pc, 0x4, tmp);
498 		tmp = ssb_pcie_read(pc, 0x100);
500 		ssb_pcie_write(pc, 0x100, tmp);
506 		ssb_pcie_mdio_write(pc, serdes_rx_device,
508 		ssb_pcie_mdio_write(pc, serdes_rx_device,
510 		ssb_pcie_mdio_write(pc, serdes_rx_device,
514 		ssb_pcicore_serdes_workaround(pc);
522 		tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
524 			pcicore_write16(pc, SSB_PCICORE_SPROM(5),
533 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
535 	struct ssb_device *pdev = pc->dev;
539 		ssb_pcicore_fix_sprom_core_index(pc);
545 	if (pc->dev->id.coreid == SSB_DEV_PCIE) {
546 		ssb_pcicore_serdes_workaround(pc);
552 void ssb_pcicore_init(struct ssb_pcicore *pc)
554 	struct ssb_device *dev = pc->dev;
562 	pc->hostmode = pcicore_is_in_hostmode(pc);
563 	if (pc->hostmode)
564 		ssb_pcicore_init_hostmode(pc);
566 	if (!pc->hostmode)
567 		ssb_pcicore_init_clientmode(pc);
570 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
572 	pcicore_write32(pc, 0x130, address);
573 	return pcicore_read32(pc, 0x134);
576 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
578 	pcicore_write32(pc, 0x130, address);
579 	pcicore_write32(pc, 0x134, data);
582 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
594 	pcicore_write32(pc, mdio_data, v);
598 		v = pcicore_read32(pc, mdio_control);
605 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
616 	pcicore_write32(pc, mdio_control, v);
618 	if (pc->dev->id.revision >= 10) {
620 		ssb_pcie_mdio_set_phy(pc, device);
626 	if (pc->dev->id.revision < 10)
629 	pcicore_write32(pc, mdio_data, v);
633 		v = pcicore_read32(pc, mdio_control);
636 			ret = pcicore_read32(pc, mdio_data);
641 	pcicore_write32(pc, mdio_control, 0);
645 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
656 	pcicore_write32(pc, mdio_control, v);
658 	if (pc->dev->id.revision >= 10) {
660 		ssb_pcie_mdio_set_phy(pc, device);
666 	if (pc->dev->id.revision < 10)
670 	pcicore_write32(pc, mdio_data, v);
674 		v = pcicore_read32(pc, mdio_control);
679 	pcicore_write32(pc, mdio_control, 0);
682 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
685 	struct ssb_device *pdev = pc->dev;
730 	if (pc->setup_done)
733 		ssb_pcicore_pci_setup_workarounds(pc);
736 		ssb_pcicore_pcie_setup_workarounds(pc);
738 	pc->setup_done = 1;