Lines Matching refs:cc
32 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
36 value |= chipco_read32(cc, offset) & ~mask;
37 chipco_write32(cc, offset, value);
42 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
45 struct ssb_device *ccdev = cc->dev;
57 if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
69 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
74 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
76 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
81 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
84 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
86 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
87 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
94 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
101 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
108 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
109 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
119 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
121 struct ssb_bus *bus = cc->dev->bus;
124 if (cc->dev->id.revision < 6) {
135 if (cc->dev->id.revision < 10) {
136 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
150 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
157 clocksrc = chipco_pctl_get_slowclksrc(cc);
158 if (cc->dev->id.revision < 6) {
169 } else if (cc->dev->id.revision < 10) {
175 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
181 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
211 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
213 struct ssb_bus *bus = cc->dev->bus;
217 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
219 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
222 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
225 if (cc->dev->id.revision >= 10) {
227 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
228 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
233 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
234 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
236 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
242 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
244 struct ssb_bus *bus = cc->dev->bus;
259 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
261 struct ssb_bus *bus = cc->dev->bus;
269 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
270 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
274 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
277 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
278 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
282 cc->fast_pwrup_delay = tmp;
285 static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
287 if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
288 return ssb_pmu_get_alp_clock(cc);
293 static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
297 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
298 if (cc->dev->id.revision < 26)
301 nb = (cc->dev->id.revision >= 37) ? 32 : 24;
313 struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
315 if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
318 return ssb_chipco_watchdog_timer_set(cc, ticks);
323 struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
326 if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
329 ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
330 return ticks / cc->ticks_per_ms;
333 static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
335 struct ssb_bus *bus = cc->dev->bus;
337 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
341 if (cc->dev->id.revision < 18)
344 return ssb_chipco_alp_clock(cc) / 1000;
348 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
350 if (!cc->dev)
353 spin_lock_init(&cc->gpio_lock);
355 if (cc->dev->id.revision >= 11)
356 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
357 dev_dbg(cc->dev->dev, "chipcommon status is 0x%x\n", cc->status);
359 if (cc->dev->id.revision >= 20) {
360 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
361 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
364 ssb_pmu_init(cc);
365 chipco_powercontrol_init(cc);
366 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
367 calc_fast_powerup_delay(cc);
369 if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
370 cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
371 cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
375 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
377 if (!cc->dev)
379 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
382 void ssb_chipco_resume(struct ssb_chipcommon *cc)
384 if (!cc->dev)
386 chipco_powercontrol_init(cc);
387 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
391 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
394 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
395 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
401 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
405 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
408 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
414 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
417 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
418 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
421 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
424 if (cc->dev->bus->chip_id != 0x5365) {
425 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
430 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
434 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
437 struct ssb_device *dev = cc->dev;
442 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
446 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
454 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
458 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
466 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
471 u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
476 maxt = ssb_chipco_watchdog_get_max_timer(cc);
477 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
482 chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
485 ssb_chipco_set_clockmode(cc, clkmode);
489 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
494 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
496 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
499 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
501 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
504 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
506 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
509 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
514 spin_lock_irqsave(&cc->gpio_lock, flags);
515 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
516 spin_unlock_irqrestore(&cc->gpio_lock, flags);
521 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
526 spin_lock_irqsave(&cc->gpio_lock, flags);
527 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
528 spin_unlock_irqrestore(&cc->gpio_lock, flags);
533 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
538 spin_lock_irqsave(&cc->gpio_lock, flags);
539 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
540 spin_unlock_irqrestore(&cc->gpio_lock, flags);
546 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
551 spin_lock_irqsave(&cc->gpio_lock, flags);
552 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
553 spin_unlock_irqrestore(&cc->gpio_lock, flags);
558 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
563 spin_lock_irqsave(&cc->gpio_lock, flags);
564 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
565 spin_unlock_irqrestore(&cc->gpio_lock, flags);
570 u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
575 if (cc->dev->id.revision < 20)
578 spin_lock_irqsave(&cc->gpio_lock, flags);
579 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
580 spin_unlock_irqrestore(&cc->gpio_lock, flags);
585 u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
590 if (cc->dev->id.revision < 20)
593 spin_lock_irqsave(&cc->gpio_lock, flags);
594 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
595 spin_unlock_irqrestore(&cc->gpio_lock, flags);
601 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
604 struct ssb_bus *bus = cc->dev->bus;
610 unsigned int ccrev = cc->dev->id.revision;
612 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
613 irq = ssb_mips_irq(cc->dev);
618 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
619 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
627 chipco_write32(cc, SSB_CHIPCO_CORECTL,
628 chipco_read32(cc, SSB_CHIPCO_CORECTL)
631 baud_base = ssb_chipco_alp_clock(cc);
635 chipco_write32(cc, SSB_CHIPCO_CORECTL,
636 chipco_read32(cc, SSB_CHIPCO_CORECTL)
640 chipco_write32(cc, SSB_CHIPCO_CORECTL,
641 chipco_read32(cc, SSB_CHIPCO_CORECTL)
645 chipco_write32(cc, SSB_CHIPCO_CORECTL,
646 chipco_read32(cc, SSB_CHIPCO_CORECTL)
652 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
662 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
663 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
675 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
680 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);