drivers/spi/spi-zynqmp-gqspi.c

356 	u32 config_reg, baud_rate_val = 0;
379 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
380 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
382 	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
384 	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
386 	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
388 	config_reg |= GQSPI_CFG_WP_HOLD_MASK;
390 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
393 		config_reg |= GQSPI_CFG_CLK_PHA_MASK;
395 		config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
398 		config_reg |= GQSPI_CFG_CLK_POL_MASK;
400 		config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
409 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
410 	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
412 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
559 	u32 config_reg, req_speed_hz, baud_rate_val = 0;
576 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
578 		config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
579 		config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
580 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
747 	u32 config_reg, genfifoentry;
761 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
762 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
763 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
848 	u32 rx_bytes, rx_rem, config_reg;
855 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
856 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
857 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
882 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
883 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
884 	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
885 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
908 	u32 config_reg;
913 		config_reg = zynqmp_gqspi_read(xqspi,
915 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
917 				   config_reg);