Lines Matching defs:config_reg
183 u32 config_reg;
189 config_reg = 0;
192 config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;
194 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
202 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
203 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
210 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
214 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
294 u32 config_reg;
298 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);
300 config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;
302 config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;
304 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
308 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
310 config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
312 config_reg |= ZYNQ_QSPI_CONFIG_PCS;
314 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
336 u32 config_reg, baud_rate_val = 0;
341 * into the configuration register (config_reg[5:3])
352 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
355 config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
358 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
360 config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
362 config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
363 config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
364 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);