drivers/spi/spi-ti-qspi.c

126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
129 	return readl(qspi->base + reg);
132 static inline void ti_qspi_write(struct ti_qspi *qspi,
135 	writel(val, qspi->base + reg);
140 	struct ti_qspi	*qspi = spi_controller_get_devdata(spi->controller);
144 		dev_dbg(qspi->dev, "host busy doing other transfers\n");
148 	if (!qspi->host->max_speed_hz) {
149 		dev_err(qspi->dev, "spi max frequency not defined\n");
153 	spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz);
155 	ret = pm_runtime_resume_and_get(qspi->dev);
157 		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
161 	pm_runtime_mark_last_busy(qspi->dev);
162 	ret = pm_runtime_put_autosuspend(qspi->dev);
164 		dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
171 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
173 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
177 	clk_rate = clk_get_rate(qspi->fclk);
180 	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div);
182 	pm_runtime_resume_and_get(qspi->dev);
186 		clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
191 		ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
194 		ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG);
198 	pm_runtime_mark_last_busy(qspi->dev);
199 	pm_runtime_put_autosuspend(qspi->dev);
202 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
204 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
206 	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
209 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
214 	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217 		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
220 	WARN(stat & BUSY, "qspi busy\n");
224 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
230 		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
236 	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
242 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
251 	cmd = qspi->cmd | QSPI_WR_SNGL;
256 		if (qspi_is_busy(qspi))
261 			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
262 					cmd, qspi->dc, *txbuf);
267 				writel(data, qspi->base +
270 				writel(data, qspi->base +
273 				writel(data, qspi->base +
276 				writel(data, qspi->base +
281 				writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
282 				cmd = qspi->cmd | QSPI_WR_SNGL;
288 			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
289 					cmd, qspi->dc, *txbuf);
290 			writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
293 			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
294 					cmd, qspi->dc, *txbuf);
295 			writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
299 		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
300 		if (ti_qspi_poll_wc(qspi)) {
301 			dev_err(qspi->dev, "write timed out\n");
311 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
321 	cmd = qspi->cmd;
337 		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
338 		if (qspi_is_busy(qspi))
361 		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
362 		if (ti_qspi_poll_wc(qspi)) {
363 			dev_err(qspi->dev, "read timed out\n");
375 				rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
377 				rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
379 				rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
381 				rx = readl(qspi->base + QSPI_SPI_DATA_REG);
385 				rx = readl(qspi->base + QSPI_SPI_DATA_REG);
397 			*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
400 			*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
410 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
416 		ret = qspi_write_msg(qspi, t, count);
418 			dev_dbg(qspi->dev, "Error while writing\n");
424 		ret = qspi_read_msg(qspi, t, count);
426 			dev_dbg(qspi->dev, "Error while reading\n");
436 	struct ti_qspi *qspi = param;
438 	complete(&qspi->transfer_complete);
441 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
444 	struct dma_chan *chan = qspi->rx_chan;
453 		dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
458 	tx->callback_param = qspi;
460 	reinit_completion(&qspi->transfer_complete);
464 		dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
469 	time_left = wait_for_completion_timeout(&qspi->transfer_complete,
473 		dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
480 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
483 	dma_addr_t dma_src = qspi->mmap_phys_base + offs;
494 		ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
498 		memcpy(to, qspi->rx_bb_addr, xfer_len);
507 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
511 	dma_addr_t dma_src = qspi->mmap_phys_base + from;
518 		ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
529 	struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
531 	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
532 	if (qspi->ctrl_base) {
533 		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
537 	qspi->mmap_enabled = true;
538 	qspi->current_cs = spi_get_chipselect(spi, 0);
543 	struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
545 	ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
546 	if (qspi->ctrl_base)
547 		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
549 	qspi->mmap_enabled = false;
550 	qspi->current_cs = -1;
557 	struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
573 	ti_qspi_write(qspi, memval,
579 	struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
583 		if (op->addr.val < qspi->mmap_size) {
585 			if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
586 				max_len = qspi->mmap_size - op->addr.val;
609 	struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
620 	if (from + op->data.nbytes > qspi->mmap_size)
623 	mutex_lock(&qspi->list_lock);
625 	if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) {
626 		ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz);
632 	if (qspi->rx_chan) {
638 			ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
642 			ret = ti_qspi_dma_bounce_buffer(qspi, from,
647 		memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
651 	mutex_unlock(&qspi->list_lock);
664 	struct ti_qspi *qspi = spi_controller_get_devdata(host);
672 	qspi->dc = 0;
675 		qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0));
677 		qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0));
679 		qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));
687 	qspi->cmd = 0;
688 	qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0));
689 	qspi->cmd |= QSPI_FLEN(frame_len_words);
691 	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
693 	mutex_lock(&qspi->list_lock);
695 	if (qspi->mmap_enabled)
699 		qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
705 		ti_qspi_setup_clk(qspi, t->speed_hz);
706 		ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
708 			dev_dbg(qspi->dev, "transfer message failed\n");
709 			mutex_unlock(&qspi->list_lock);
719 	mutex_unlock(&qspi->list_lock);
721 	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
730 	struct ti_qspi      *qspi;
732 	qspi = dev_get_drvdata(dev);
733 	ti_qspi_restore_ctx(qspi);
738 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
740 	if (qspi->rx_bb_addr)
741 		dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
742 				  qspi->rx_bb_addr,
743 				  qspi->rx_bb_dma_addr);
745 	if (qspi->rx_chan)
746 		dma_release_channel(qspi->rx_chan);
750 	{.compatible = "ti,dra7xxx-qspi" },
751 	{.compatible = "ti,am4372-qspi" },
758 	struct  ti_qspi *qspi;
766 	host = spi_alloc_host(&pdev->dev, sizeof(*qspi));
784 	qspi = spi_controller_get_devdata(host);
785 	qspi->host = host;
786 	qspi->dev = &pdev->dev;
787 	platform_set_drvdata(pdev, qspi);
810 		qspi->mmap_size = resource_size(res_mmap);
818 	mutex_init(&qspi->list_lock);
820 	qspi->base = devm_ioremap_resource(&pdev->dev, r);
821 	if (IS_ERR(qspi->base)) {
822 		ret = PTR_ERR(qspi->base);
828 		qspi->ctrl_base =
831 		if (IS_ERR(qspi->ctrl_base)) {
832 			ret = PTR_ERR(qspi->ctrl_base);
837 						 1, &qspi->ctrl_reg);
845 	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
846 	if (IS_ERR(qspi->fclk)) {
847 		ret = PTR_ERR(qspi->fclk);
861 	qspi->rx_chan = dma_request_chan_by_mask(&mask);
862 	if (IS_ERR(qspi->rx_chan)) {
863 		dev_err(qspi->dev,
865 		qspi->rx_chan = NULL;
869 	qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
871 					      &qspi->rx_bb_dma_addr,
873 	if (!qspi->rx_bb_addr) {
874 		dev_err(qspi->dev,
876 		dma_release_channel(qspi->rx_chan);
879 	host->dma_rx = qspi->rx_chan;
880 	init_completion(&qspi->transfer_complete);
882 		qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
885 	if (!qspi->rx_chan && res_mmap) {
886 		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
887 		if (IS_ERR(qspi->mmap_base)) {
890 				 PTR_ERR(qspi->mmap_base));
891 			qspi->mmap_base = NULL;
895 	qspi->mmap_enabled = false;
896 	qspi->current_cs = -1;
902 	ti_qspi_dma_cleanup(qspi);
912 	struct ti_qspi *qspi = platform_get_drvdata(pdev);
915 	rc = spi_controller_suspend(qspi->host);
925 	ti_qspi_dma_cleanup(qspi);
936 		.name	= "ti-qspi",
947 MODULE_ALIAS("platform:ti-qspi");