drivers/spi/spi-sh.c

81 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
84 	if (ss->width == 8)
85 		iowrite8(data, ss->addr + (offset >> 2));
86 	else if (ss->width == 32)
87 		iowrite32(data, ss->addr + offset);
90 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
92 	if (ss->width == 8)
93 		return ioread8(ss->addr + (offset >> 2));
94 	else if (ss->width == 32)
95 		return ioread32(ss->addr + offset);
100 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
105 	tmp = spi_sh_read(ss, offset);
107 	spi_sh_write(ss, tmp, offset);
110 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
115 	tmp = spi_sh_read(ss, offset);
117 	spi_sh_write(ss, tmp, offset);
120 static void clear_fifo(struct spi_sh_data *ss)
122 	spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
123 	spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
126 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
130 	while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
138 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
142 	while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
150 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
160 		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
166 				!(spi_sh_read(ss, SPI_SH_CR4) &
168 				!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
170 			spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
172 		if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
174 			spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
185 			ss->cr1 &= ~SPI_SH_TBE;
186 			spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
187 			ret = wait_event_interruptible_timeout(ss->wait,
188 						 ss->cr1 & SPI_SH_TBE,
190 			if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
198 		spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
199 		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
201 		ss->cr1 &= ~SPI_SH_TBE;
202 		spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
203 		ret = wait_event_interruptible_timeout(ss->wait,
204 					 ss->cr1 & SPI_SH_TBE,
206 		if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
215 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
225 		spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
227 		spi_sh_write(ss, t->len, SPI_SH_CR3);
229 	spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
230 	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
232 	spi_sh_wait_write_buffer_empty(ss);
237 			ss->cr1 &= ~SPI_SH_RBF;
238 			spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
239 			ret = wait_event_interruptible_timeout(ss->wait,
240 						 ss->cr1 & SPI_SH_RBF,
243 			    spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
251 			if (spi_sh_wait_receive_buffer(ss))
253 			data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
262 		clear_fifo(ss);
263 		spi_sh_write(ss, 1, SPI_SH_CR3);
265 		spi_sh_write(ss, 0, SPI_SH_CR3);
274 	struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
280 	spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
289 			ret = spi_sh_send(ss, mesg, t);
294 			ret = spi_sh_receive(ss, mesg, t);
304 	clear_fifo(ss);
305 	spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
308 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
311 	clear_fifo(ss);
321 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
323 	clear_fifo(ss);
330 	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
334 	spi_sh_write(ss, 0xfe, SPI_SH_CR1);	/* SPI sycle stop */
335 	spi_sh_write(ss, 0x00, SPI_SH_CR1);	/* CR1 init */
336 	spi_sh_write(ss, 0x00, SPI_SH_CR3);	/* CR3 init */
338 	clear_fifo(ss);
341 	spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
349 	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
353 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
359 	struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
362 	cr1 = spi_sh_read(ss, SPI_SH_CR1);
364 		ss->cr1 |= SPI_SH_TBE;
366 		ss->cr1 |= SPI_SH_TBF;
368 		ss->cr1 |= SPI_SH_RBE;
370 		ss->cr1 |= SPI_SH_RBF;
372 	if (ss->cr1) {
373 		spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
374 		wake_up(&ss->wait);
382 	struct spi_sh_data *ss = platform_get_drvdata(pdev);
384 	spi_unregister_controller(ss->host);
385 	free_irq(ss->irq, ss);
392 	struct spi_sh_data *ss;
412 	ss = spi_controller_get_devdata(host);
413 	platform_set_drvdata(pdev, ss);
417 		ss->width = 8;
420 		ss->width = 32;
426 	ss->irq = irq;
427 	ss->host = host;
428 	ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
429 	if (ss->addr == NULL) {
433 	init_waitqueue_head(&ss->wait);
435 	ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
456 	free_irq(irq, ss);