drivers/spi/spi-s3c64xx.c

17 #include <linux/platform_data/spi-s3c64xx.h>
20 #include <linux/spi/spi.h>
158  * differ in some aspects such as the size of the fifo and spi bus clock
180  * @clk: Pointer to the spi clock.
353 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
356 					spi_controller_get_devdata(spi->controller);
378 static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi)
380 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
402 	spi->dma_rx = sdd->rx_dma.ch;
403 	spi->dma_tx = sdd->tx_dma.ch;
408 static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi)
410 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
427 				struct spi_device *spi,
776 	struct spi_device *spi = msg->spi;
777 	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
789 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
791 	struct spi_controller *ctlr = spi->controller;
797 				    struct spi_device *spi,
823 		sdd->cur_mode = spi->mode;
879 		s3c64xx_spi_set_cs(spi, true);
886 			dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
896 			dev_err(&spi->dev,
910 					dev_err(&spi->dev, "TX residue: %d\n", s.residue);
917 					dev_err(&spi->dev, "RX residue: %d\n", s.residue);
950 				struct spi_device *spi)
956 	target_np = spi->dev.of_node;
958 		dev_err(&spi->dev, "device node not found\n");
969 		dev_info(&spi->dev, "feedback delay set to default (0)\n");
973 	of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
984 static int s3c64xx_spi_setup(struct spi_device *spi)
986 	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
991 	sdd = spi_controller_get_devdata(spi->controller);
992 	if (spi->dev.of_node) {
993 		cs = s3c64xx_get_target_ctrldata(spi);
994 		spi->controller_data = cs;
999 		dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
1003 	if (!spi_get_ctldata(spi))
1004 		spi_set_ctldata(spi, cs);
1017 		if (spi->max_speed_hz > speed)
1018 			spi->max_speed_hz = speed;
1020 		psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
1026 		if (spi->max_speed_hz < speed) {
1036 		if (spi->max_speed_hz >= speed) {
1037 			spi->max_speed_hz = speed;
1039 			dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1040 				spi->max_speed_hz);
1048 	s3c64xx_spi_set_cs(spi, false);
1056 	s3c64xx_spi_set_cs(spi, false);
1058 	spi_set_ctldata(spi, NULL);
1061 	if (spi->dev.of_node)
1067 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1069 	struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1072 	if (spi->dev.of_node)
1075 	spi_set_ctldata(spi, NULL);
1081 	struct spi_controller *spi = sdd->host;
1088 		dev_err(&spi->dev, "RX overrun\n");
1092 		dev_err(&spi->dev, "RX underrun\n");
1096 		dev_err(&spi->dev, "TX overrun\n");
1100 		dev_err(&spi->dev, "TX underrun\n");
1168 	if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1169 		dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1214 		ret = of_alias_get_id(pdev->dev.of_node, "spi");
1313 	/* the spi->mode bits understood by this driver: */
1331 	sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi");
1334 				     "Unable to acquire clock 'spi'\n");
1363 				"spi-s3c64xx", sdd);
1632 		.name		= "s3c2443-spi",
1635 		.name		= "s3c6410-spi",
1642 	{ .compatible = "google,gs101-spi",
1645 	{ .compatible = "samsung,s3c2443-spi",
1648 	{ .compatible = "samsung,s3c6410-spi",
1651 	{ .compatible = "samsung,s5pv210-spi",
1654 	{ .compatible = "samsung,exynos4210-spi",
1657 	{ .compatible = "samsung,exynos7-spi",
1660 	{ .compatible = "samsung,exynos5433-spi",
1663 	{ .compatible = "samsung,exynos850-spi",
1666 	{ .compatible = "samsung,exynosautov9-spi",
1669 	{ .compatible = "tesla,fsd-spi",
1678 		.name	= "s3c64xx-spi",
1686 MODULE_ALIAS("platform:s3c64xx-spi");