drivers/spi/spi-rzv2m-csi.c

114 static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi,
123 	tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value;
124 	writel(tmp, csi->base + reg_offs);
127 static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert)
131 	rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert);
136 	return readl_poll_timeout(csi->base + CSI_MODE, reg,
141 static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi,
146 	rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable);
151 	return readl_poll_timeout(csi->base + CSI_MODE, reg,
156 static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi)
160 	if (readl(csi->base + CSI_OFIFOL))
163 	if (csi->bytes_per_word == 2) {
164 		const u16 *buf = csi->txbuf;
166 		for (i = 0; i < csi->words_to_transfer; i++)
167 			writel(buf[i], csi->base + CSI_OFIFO);
169 		const u8 *buf = csi->txbuf;
171 		for (i = 0; i < csi->words_to_transfer; i++)
172 			writel(buf[i], csi->base + CSI_OFIFO);
175 	csi->txbuf += csi->bytes_to_transfer;
176 	csi->bytes_sent += csi->bytes_to_transfer;
181 static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi)
185 	if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer)
188 	if (csi->bytes_per_word == 2) {
189 		u16 *buf = csi->rxbuf;
191 		for (i = 0; i < csi->words_to_transfer; i++)
192 			buf[i] = (u16)readl(csi->base + CSI_IFIFO);
194 		u8 *buf = csi->rxbuf;
196 		for (i = 0; i < csi->words_to_transfer; i++)
197 			buf[i] = (u8)readl(csi->base + CSI_IFIFO);
200 	csi->rxbuf += csi->bytes_to_transfer;
201 	csi->bytes_received += csi->bytes_to_transfer;
206 static inline void rzv2m_csi_empty_rxfifo(struct rzv2m_csi_priv *csi)
210 	for (i = 0; i < csi->words_to_transfer; i++)
211 		readl(csi->base + CSI_IFIFO);
214 static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi)
216 	unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent);
217 	unsigned int bytes_remaining = csi->buffer_len - bytes_transferred;
220 	if (csi->txbuf)
230 	if (csi->bytes_per_word == 2)
239 	csi->words_to_transfer = rounddown_pow_of_two(to_transfer);
241 	if (csi->bytes_per_word == 2)
242 		csi->bytes_to_transfer = csi->words_to_transfer << 1;
244 		csi->bytes_to_transfer = csi->words_to_transfer;
247 static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi)
249 	rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG,
250 				ilog2(csi->words_to_transfer));
253 static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi,
256 	rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable);
259 static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi,
262 	u32 cnt = readl(csi->base + CSI_CNT);
264 	writel(cnt & ~enable_bits, csi->base + CSI_CNT);
267 static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi)
269 	rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E |
274 static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs)
276 	writel(irqs, csi->base + CSI_INT);
279 static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi)
281 	rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF |
286 static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits)
288 	u32 cnt = readl(csi->base + CSI_CNT);
290 	writel(cnt | enable_bits, csi->base + CSI_CNT);
293 static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi,
298 	rzv2m_csi_enable_irqs(csi, enable_bits);
300 	if (spi_controller_is_target(csi->controller)) {
301 		ret = wait_event_interruptible(csi->wait,
302 				((csi->status & wait_mask) == wait_mask) ||
303 				csi->errors || csi->target_aborted);
304 		if (ret || csi->target_aborted)
307 		ret = wait_event_timeout(csi->wait,
308 				((csi->status & wait_mask) == wait_mask) ||
309 				csi->errors, HZ) == 0 ? -ETIMEDOUT : 0;
312 	rzv2m_csi_disable_irqs(csi, enable_bits);
314 	if (csi->errors)
320 static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi)
324 	if (readl(csi->base + CSI_IFIFOL) >= csi->bytes_to_transfer)
327 	ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR,
330 		csi->errors |= RX_TIMEOUT_ERROR;
337 	struct rzv2m_csi_priv *csi = data;
339 	csi->status = readl(csi->base + CSI_INT);
340 	rzv2m_csi_disable_irqs(csi, csi->status);
342 	if (csi->status & CSI_INT_OVERF)
343 		csi->errors |= OVERFLOW_ERROR;
344 	if (csi->status & CSI_INT_UNDER)
345 		csi->errors |= UNDERRUN_ERROR;
347 	wake_up(&csi->wait);
352 static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz)
354 	unsigned long csiclk_rate = clk_get_rate(csi->csiclk);
355 	unsigned long pclk_rate = clk_get_rate(csi->pclk);
364 		clk_set_rate(csi->csiclk, csiclk_rate >> 1);
365 		csiclk_rate = clk_get_rate(csi->csiclk);
367 		clk_set_rate(csi->csiclk, csiclk_rate << 1);
368 		csiclk_rate = clk_get_rate(csi->csiclk);
377 	dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1));
379 	rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks);
382 static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi,
387 		rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0);
390 		rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1);
392 	csi->bytes_per_word = t->bits_per_word / 8;
393 	rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL,
394 				csi->bytes_per_word == 2);
399 	struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
403 	rzv2m_csi_sw_reset(csi, 0);
405 	writel(CSI_MODE_SETUP, csi->base + CSI_MODE);
408 	rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_MODE,
412 	rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,
416 	rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE,
417 				!!spi_controller_is_target(csi->controller));
419 	if (csi->use_ss_pin)
425 	rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SS, slave_selection);
428 	ret = rzv2m_csi_sw_reset(csi, 1);
431 	rzv2m_csi_sw_reset(csi, 0);
437 	rzv2m_csi_start_stop_operation(csi, 1, false);
439 	rzv2m_csi_start_stop_operation(csi, 0, false);
444 static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
446 	bool tx_completed = !csi->txbuf;
447 	bool rx_completed = !csi->rxbuf;
451 	writel(0, csi->base + CSI_OFIFOL);
454 	writel(0, csi->base + CSI_IFIFOL);
456 	csi->bytes_sent = 0;
457 	csi->bytes_received = 0;
458 	csi->errors = 0;
459 	csi->target_aborted = false;
461 	rzv2m_csi_disable_all_irqs(csi);
462 	rzv2m_csi_clear_all_irqs(csi);
463 	rzv2m_csi_enable_rx_trigger(csi, true);
473 		rzv2m_csi_calc_current_transfer(csi);
474 		rzv2m_csi_set_rx_fifo_trigger_level(csi);
476 		rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER);
478 		writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
479 		csi->status = 0;
482 		if (csi->txbuf) {
483 			ret = rzv2m_csi_fill_txfifo(csi);
487 			if (csi->bytes_sent == csi->buffer_len)
491 		rzv2m_csi_start_stop_operation(csi, 1, false);
496 		 * csi->rxbuf.
498 		ret = rzv2m_csi_wait_for_rx_ready(csi);
502 		if (!spi_controller_is_target(csi->controller))
503 			rzv2m_csi_start_stop_operation(csi, 0, false);
506 		if (csi->rxbuf) {
507 			ret = rzv2m_csi_read_rxfifo(csi);
511 			if (csi->bytes_received == csi->buffer_len)
514 			rzv2m_csi_empty_rxfifo(csi);
517 		if (csi->errors) {
523 	rzv2m_csi_start_stop_operation(csi, 0, true);
524 	rzv2m_csi_disable_all_irqs(csi);
525 	rzv2m_csi_enable_rx_trigger(csi, false);
526 	rzv2m_csi_clear_all_irqs(csi);
535 	struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller);
536 	struct device *dev = csi->dev;
539 	csi->txbuf = transfer->tx_buf;
540 	csi->rxbuf = transfer->rx_buf;
541 	csi->buffer_len = transfer->len;
543 	rzv2m_csi_setup_operating_mode(csi, transfer);
545 	if (!spi_controller_is_target(csi->controller))
546 		rzv2m_csi_setup_clock(csi, transfer->speed_hz);
548 	ret = rzv2m_csi_pio_transfer(csi);
550 		if (csi->errors & UNDERRUN_ERROR)
552 		if (csi->errors & OVERFLOW_ERROR)
554 		if (csi->errors & TX_TIMEOUT_ERROR)
556 		if (csi->errors & RX_TIMEOUT_ERROR)
565 	struct rzv2m_csi_priv *csi = spi_controller_get_devdata(ctlr);
567 	csi->target_aborted = true;
568 	wake_up(&csi->wait);
578 	struct rzv2m_csi_priv *csi;
587 		controller = devm_spi_alloc_target(dev, sizeof(*csi));
589 		controller = devm_spi_alloc_host(dev, sizeof(*csi));
594 	csi = spi_controller_get_devdata(controller);
595 	platform_set_drvdata(pdev, csi);
597 	csi->use_ss_pin = false;
599 	    !of_property_read_bool(np, "renesas,csi-no-ss"))
600 		csi->use_ss_pin = true;
602 	csi->dev = dev;
603 	csi->controller = controller;
604 	csi->target_aborted = false;
606 	csi->base = devm_platform_ioremap_resource(pdev, 0);
607 	if (IS_ERR(csi->base))
608 		return PTR_ERR(csi->base);
614 	csi->csiclk = devm_clk_get(dev, "csiclk");
615 	if (IS_ERR(csi->csiclk))
616 		return dev_err_probe(dev, PTR_ERR(csi->csiclk),
619 	csi->pclk = devm_clk_get(dev, "pclk");
620 	if (IS_ERR(csi->pclk))
621 		return dev_err_probe(dev, PTR_ERR(csi->pclk),
628 	init_waitqueue_head(&csi->wait);
640 			       dev_name(dev), csi);
652 	ret = rzv2m_csi_sw_reset(csi, 1);
656 	ret = clk_prepare_enable(csi->csiclk);
662 		clk_disable_unprepare(csi->csiclk);
671 	struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev);
673 	spi_unregister_controller(csi->controller);
674 	rzv2m_csi_sw_reset(csi, 1);
675 	clk_disable_unprepare(csi->csiclk);
679 	{ .compatible = "renesas,rzv2m-csi" },