drivers/spi/spi-pl022.c

1484 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1486 	return rate / (cpsdvsr * (1 + scr));
1493 	u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1500 	/* cpsdvsr = 254 & scr = 255 */
1517 	 * freq) for all values of scr & cpsdvsr.
1519 	while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1521 			tmp = spi_rate(rate, cpsdvsr, scr);
1535 				best_cpsdvsr = cpsdvsr;
1547 		cpsdvsr += 2;
1551 	WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1554 	clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1559 	dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1560 		clk_freq->cpsdvsr, clk_freq->scr);
1598 	struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1657 	if ((0 == chip_info->clk_freq.cpsdvsr)
1666 		if ((clk_freq.cpsdvsr % 2) != 0)
1667 			clk_freq.cpsdvsr =
1668 				clk_freq.cpsdvsr - 1;
1670 	if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1671 	    || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1674 			"cpsdvsr is configured incorrectly\n");
1736 	chip->cpsr = clk_freq.cpsdvsr;