Lines Matching defs:pl022
27 #include <linux/amba/pl022.h>
333 * struct pl022 - This is the private SSP driver data structure
360 struct pl022 {
421 * @pl022: SSP driver private data structure
428 static void internal_cs_control(struct pl022 *pl022, bool enable)
432 tmp = readw(SSP_CSR(pl022->virtbase));
434 tmp &= ~BIT(pl022->cur_cs);
436 tmp |= BIT(pl022->cur_cs);
437 writew(tmp, SSP_CSR(pl022->virtbase));
442 struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
443 if (pl022->vendor->internal_cs_ctrl)
444 internal_cs_control(pl022, enable);
449 * @pl022: SSP driver private data structure
451 static int flush(struct pl022 *pl022)
455 dev_dbg(&pl022->adev->dev, "flush\n");
457 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
458 readw(SSP_DR(pl022->virtbase));
459 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
461 pl022->exp_fifo_level = 0;
468 * @pl022: SSP driver private data structure
470 static void restore_state(struct pl022 *pl022)
472 struct chip_data *chip = pl022->cur_chip;
474 if (pl022->vendor->extended_cr)
475 writel(chip->cr0, SSP_CR0(pl022->virtbase));
477 writew(chip->cr0, SSP_CR0(pl022->virtbase));
478 writew(chip->cr1, SSP_CR1(pl022->virtbase));
479 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
480 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
481 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
482 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
558 * @pl022: SSP driver private data structure
560 static void load_ssp_default_config(struct pl022 *pl022)
562 if (pl022->vendor->pl023) {
563 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
564 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
565 } else if (pl022->vendor->extended_cr) {
566 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
567 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
569 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
570 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
572 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
573 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
574 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
575 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
580 * set in pl022.
582 static void readwriter(struct pl022 *pl022)
595 dev_dbg(&pl022->adev->dev,
597 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
600 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
601 && (pl022->rx < pl022->rx_end)) {
602 switch (pl022->read) {
604 readw(SSP_DR(pl022->virtbase));
607 *(u8 *) (pl022->rx) =
608 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
611 *(u16 *) (pl022->rx) =
612 (u16) readw(SSP_DR(pl022->virtbase));
615 *(u32 *) (pl022->rx) =
616 readl(SSP_DR(pl022->virtbase));
619 pl022->rx += (pl022->cur_chip->n_bytes);
620 pl022->exp_fifo_level--;
625 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
626 && (pl022->tx < pl022->tx_end)) {
627 switch (pl022->write) {
629 writew(0x0, SSP_DR(pl022->virtbase));
632 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
635 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
638 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
641 pl022->tx += (pl022->cur_chip->n_bytes);
642 pl022->exp_fifo_level++;
649 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
650 && (pl022->rx < pl022->rx_end)) {
651 switch (pl022->read) {
653 readw(SSP_DR(pl022->virtbase));
656 *(u8 *) (pl022->rx) =
657 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
660 *(u16 *) (pl022->rx) =
661 (u16) readw(SSP_DR(pl022->virtbase));
664 *(u32 *) (pl022->rx) =
665 readl(SSP_DR(pl022->virtbase));
668 pl022->rx += (pl022->cur_chip->n_bytes);
669 pl022->exp_fifo_level--;
683 static void unmap_free_dma_scatter(struct pl022 *pl022)
686 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
687 pl022->sgt_tx.nents, DMA_TO_DEVICE);
688 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
689 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
690 sg_free_table(&pl022->sgt_rx);
691 sg_free_table(&pl022->sgt_tx);
696 struct pl022 *pl022 = data;
698 BUG_ON(!pl022->sgt_rx.sgl);
711 dma_sync_sg_for_cpu(&pl022->adev->dev,
712 pl022->sgt_rx.sgl,
713 pl022->sgt_rx.nents,
716 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
717 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
726 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
727 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
739 unmap_free_dma_scatter(pl022);
741 spi_finalize_current_transfer(pl022->host);
744 static void setup_dma_scatter(struct pl022 *pl022,
771 dev_dbg(&pl022->adev->dev,
782 sg_set_page(sg, virt_to_page(pl022->dummypage),
785 dev_dbg(&pl022->adev->dev,
796 * @pl022: SSP driver's private data structure
798 static int configure_dma(struct pl022 *pl022)
801 .src_addr = SSP_DR(pl022->phybase),
806 .dst_addr = SSP_DR(pl022->phybase),
813 struct dma_chan *rxchan = pl022->dma_rx_channel;
814 struct dma_chan *txchan = pl022->dma_tx_channel;
828 switch (pl022->rx_lev_trig) {
845 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
849 switch (pl022->tx_lev_trig) {
866 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
870 switch (pl022->read) {
886 switch (pl022->write) {
913 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
914 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
916 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
920 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
925 setup_dma_scatter(pl022, pl022->rx,
926 pl022->cur_transfer->len, &pl022->sgt_rx);
927 setup_dma_scatter(pl022, pl022->tx,
928 pl022->cur_transfer->len, &pl022->sgt_tx);
931 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
932 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
936 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
937 pl022->sgt_tx.nents, DMA_TO_DEVICE);
943 pl022->sgt_rx.sgl,
951 pl022->sgt_tx.sgl,
960 rxdesc->callback_param = pl022;
967 pl022->dma_running = true;
975 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
976 pl022->sgt_tx.nents, DMA_TO_DEVICE);
978 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
979 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
981 sg_free_table(&pl022->sgt_tx);
983 sg_free_table(&pl022->sgt_rx);
988 static int pl022_dma_probe(struct pl022 *pl022)
999 pl022->dma_rx_channel = dma_request_channel(mask,
1000 pl022->host_info->dma_filter,
1001 pl022->host_info->dma_rx_param);
1002 if (!pl022->dma_rx_channel) {
1003 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1007 pl022->dma_tx_channel = dma_request_channel(mask,
1008 pl022->host_info->dma_filter,
1009 pl022->host_info->dma_tx_param);
1010 if (!pl022->dma_tx_channel) {
1011 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1015 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1016 if (!pl022->dummypage)
1019 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1020 dma_chan_name(pl022->dma_rx_channel),
1021 dma_chan_name(pl022->dma_tx_channel));
1026 dma_release_channel(pl022->dma_tx_channel);
1028 dma_release_channel(pl022->dma_rx_channel);
1029 pl022->dma_rx_channel = NULL;
1031 dev_err(&pl022->adev->dev,
1036 static int pl022_dma_autoprobe(struct pl022 *pl022)
1038 struct device *dev = &pl022->adev->dev;
1049 pl022->dma_rx_channel = chan;
1057 pl022->dma_tx_channel = chan;
1059 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1060 if (!pl022->dummypage) {
1068 dma_release_channel(pl022->dma_tx_channel);
1069 pl022->dma_tx_channel = NULL;
1071 dma_release_channel(pl022->dma_rx_channel);
1072 pl022->dma_rx_channel = NULL;
1077 static void terminate_dma(struct pl022 *pl022)
1079 if (!pl022->dma_running)
1082 struct dma_chan *rxchan = pl022->dma_rx_channel;
1083 struct dma_chan *txchan = pl022->dma_tx_channel;
1087 unmap_free_dma_scatter(pl022);
1088 pl022->dma_running = false;
1091 static void pl022_dma_remove(struct pl022 *pl022)
1093 terminate_dma(pl022);
1094 if (pl022->dma_tx_channel)
1095 dma_release_channel(pl022->dma_tx_channel);
1096 if (pl022->dma_rx_channel)
1097 dma_release_channel(pl022->dma_rx_channel);
1098 kfree(pl022->dummypage);
1102 static inline int configure_dma(struct pl022 *pl022)
1107 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1112 static inline int pl022_dma_probe(struct pl022 *pl022)
1117 static inline void terminate_dma(struct pl022 *pl022)
1121 static inline void pl022_dma_remove(struct pl022 *pl022)
1141 struct pl022 *pl022 = dev_id;
1144 irq_status = readw(SSP_MIS(pl022->virtbase));
1159 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1160 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1161 dev_err(&pl022->adev->dev,
1170 SSP_IMSC(pl022->virtbase));
1171 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1172 writew((readw(SSP_CR1(pl022->virtbase)) &
1173 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1174 pl022->cur_transfer->error |= SPI_TRANS_FAIL_IO;
1175 spi_finalize_current_transfer(pl022->host);
1179 readwriter(pl022);
1181 if (pl022->tx == pl022->tx_end) {
1183 writew((readw(SSP_IMSC(pl022->virtbase)) &
1185 SSP_IMSC(pl022->virtbase));
1193 if (pl022->rx >= pl022->rx_end) {
1195 SSP_IMSC(pl022->virtbase));
1196 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1197 if (unlikely(pl022->rx > pl022->rx_end)) {
1198 dev_warn(&pl022->adev->dev, "read %u surplus "
1201 (u32) (pl022->rx - pl022->rx_end));
1203 spi_finalize_current_transfer(pl022->host);
1214 static int set_up_next_transfer(struct pl022 *pl022,
1220 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1222 dev_err(&pl022->adev->dev,
1225 pl022->cur_transfer->len,
1226 pl022->cur_chip->n_bytes);
1227 dev_err(&pl022->adev->dev, "skipping this message\n");
1230 pl022->tx = (void *)transfer->tx_buf;
1231 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1232 pl022->rx = (void *)transfer->rx_buf;
1233 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1234 pl022->write =
1235 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1236 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1240 static int do_interrupt_dma_transfer(struct pl022 *pl022)
1250 ret = set_up_next_transfer(pl022, pl022->cur_transfer);
1255 if (pl022->cur_chip->enable_dma) {
1257 if (configure_dma(pl022)) {
1258 dev_dbg(&pl022->adev->dev,
1267 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1268 SSP_CR1(pl022->virtbase));
1269 writew(irqflags, SSP_IMSC(pl022->virtbase));
1273 static void print_current_status(struct pl022 *pl022)
1278 if (pl022->vendor->extended_cr)
1279 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1281 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1282 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1283 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1284 read_sr = readw(SSP_SR(pl022->virtbase));
1286 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1287 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1288 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1289 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1290 dev_warn(&pl022->adev->dev,
1291 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1292 pl022->exp_fifo_level,
1293 pl022->vendor->fifodepth);
1297 static int do_polling_transfer(struct pl022 *pl022)
1303 ret = set_up_next_transfer(pl022, pl022->cur_transfer);
1307 flush(pl022);
1308 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1309 SSP_CR1(pl022->virtbase));
1311 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1314 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1316 readwriter(pl022);
1318 dev_warn(&pl022->adev->dev,
1320 print_current_status(pl022);
1332 struct pl022 *pl022 = spi_controller_get_devdata(host);
1334 pl022->cur_transfer = transfer;
1337 pl022->cur_chip = spi_get_ctldata(spi);
1338 pl022->cur_cs = spi_get_chipselect(spi, 0);
1340 restore_state(pl022);
1341 flush(pl022);
1343 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1344 return do_polling_transfer(pl022);
1346 return do_interrupt_dma_transfer(pl022);
1351 struct pl022 *pl022 = spi_controller_get_devdata(ctlr);
1353 terminate_dma(pl022);
1354 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1355 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1360 struct pl022 *pl022 = spi_controller_get_devdata(host);
1363 writew((readw(SSP_CR1(pl022->virtbase)) &
1364 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1369 static int verify_controller_parameters(struct pl022 *pl022,
1374 dev_err(&pl022->adev->dev,
1379 (!pl022->vendor->unidir)) {
1380 dev_err(&pl022->adev->dev,
1387 dev_err(&pl022->adev->dev,
1394 dev_err(&pl022->adev->dev,
1405 if (pl022->vendor->fifodepth < 16) {
1406 dev_err(&pl022->adev->dev,
1412 if (pl022->vendor->fifodepth < 32) {
1413 dev_err(&pl022->adev->dev,
1419 dev_err(&pl022->adev->dev,
1430 if (pl022->vendor->fifodepth < 16) {
1431 dev_err(&pl022->adev->dev,
1437 if (pl022->vendor->fifodepth < 32) {
1438 dev_err(&pl022->adev->dev,
1444 dev_err(&pl022->adev->dev,
1451 dev_err(&pl022->adev->dev,
1457 dev_err(&pl022->adev->dev,
1462 if (pl022->vendor->extended_cr) {
1467 dev_err(&pl022->adev->dev,
1473 dev_err(&pl022->adev->dev,
1489 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1497 rate = clk_get_rate(pl022->clk);
1504 dev_warn(&pl022->adev->dev,
1509 dev_err(&pl022->adev->dev,
1551 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1556 dev_dbg(&pl022->adev->dev,
1559 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1600 struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
1627 of_property_read_u32(np, "pl022,interface",
1629 of_property_read_u32(np, "pl022,com-mode",
1631 of_property_read_u32(np, "pl022,rx-level-trig",
1633 of_property_read_u32(np, "pl022,tx-level-trig",
1635 of_property_read_u32(np, "pl022,ctrl-len",
1637 of_property_read_u32(np, "pl022,wait-state",
1639 of_property_read_u32(np, "pl022,duplex",
1659 status = calculate_effective_freq(pl022,
1678 status = verify_controller_parameters(pl022, chip_info);
1684 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1685 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1691 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1695 pl022->vendor->max_bpw);
1720 && ((pl022->host_info)->enable_dma)) {
1739 if (pl022->vendor->extended_cr) {
1742 if (pl022->vendor->pl023) {
1795 if (pl022->vendor->loopback) {
1847 of_property_read_u32(np, "pl022,autosuspend-delay",
1849 pd->rt = of_property_read_bool(np, "pl022,rt");
1860 struct pl022 *pl022 = NULL; /*Data for this driver */
1874 host = spi_alloc_host(dev, sizeof(struct pl022));
1880 pl022 = spi_controller_get_devdata(host);
1881 pl022->host = host;
1882 pl022->host_info = platform_info;
1883 pl022->adev = adev;
1884 pl022->vendor = id->data;
1904 * always MS bit first on the original pl022.
1907 if (pl022->vendor->extended_cr)
1916 pl022->phybase = adev->res.start;
1917 pl022->virtbase = devm_ioremap(dev, adev->res.start,
1919 if (pl022->virtbase == NULL) {
1924 &adev->res.start, pl022->virtbase);
1926 pl022->clk = devm_clk_get_enabled(&adev->dev, NULL);
1927 if (IS_ERR(pl022->clk)) {
1928 status = PTR_ERR(pl022->clk);
1934 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
1935 SSP_CR1(pl022->virtbase));
1936 load_ssp_default_config(pl022);
1939 0, "pl022", pl022);
1946 status = pl022_dma_autoprobe(pl022);
1956 status = pl022_dma_probe(pl022);
1962 amba_set_drvdata(adev, pl022);
1986 pl022_dma_remove(pl022);
1999 struct pl022 *pl022 = amba_get_drvdata(adev);
2001 if (!pl022)
2010 load_ssp_default_config(pl022);
2011 if (pl022->host_info->enable_dma)
2012 pl022_dma_remove(pl022);
2020 struct pl022 *pl022 = dev_get_drvdata(dev);
2023 ret = spi_controller_suspend(pl022->host);
2029 spi_controller_resume(pl022->host);
2041 struct pl022 *pl022 = dev_get_drvdata(dev);
2049 ret = spi_controller_resume(pl022->host);
2060 struct pl022 *pl022 = dev_get_drvdata(dev);
2062 clk_disable_unprepare(pl022->clk);
2070 struct pl022 *pl022 = dev_get_drvdata(dev);
2073 clk_prepare_enable(pl022->clk);
2171 .name = "ssp-pl022",